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[Verilog-A] problem with the code (Read 721 times)
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[Verilog-A] problem with the code
Sep 19th, 2019, 12:34am
Hi, I am trying to make a pulse generator with conditional delay.
But it is not working.
Can someone help me with this?

module verilog_pulse(out);

output out;
electrical out;

parameter real fpul = 500M;
parameter real fsin = 242M;
parameter real vdd = 0.8;
parameter real t_tran = 0;
parameter real va = 1;

real p,phase,vout,t_delay;

analog begin

@(initial_step) begin

       @(timer(0, 1/fpul*0.5)) begin
         if (p==0) begin
         else if (p==1) begin

       phase = 2*`M_PI*idtmod(fsin, 0.0, 1.0, -0.5);
       t_delay = va*sin(phase);

       V(out) <+ transition(vout,t_delay,t_tran);

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Ken Kundert
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Posts: 2352
Silicon Valley
Re: [Verilog-A] problem with the code
Reply #1 - Sep 19th, 2019, 8:37am
Debugging by inserting $strobe statements should lead you to the problem I would think.  Also, it would help if you indented your code properly.

The use of idtmod is weird. You can generate the sine wave directly. No need to use idt or idtmod, which are expensive operations.

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