helpveriloga
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Hi, I am trying to make a pulse generator with conditional delay. But it is not working. Can someone help me with this?
module verilog_pulse(out);
output out; electrical out;
parameter real fpul = 500M; parameter real fsin = 242M; parameter real vdd = 0.8; parameter real t_tran = 0; parameter real va = 1;
real p,phase,vout,t_delay;
analog begin
@(initial_step) begin p=0;
@(timer(0, 1/fpul*0.5)) begin if (p==0) begin vout=0; p=1; end else if (p==1) begin vout=vdd; p=0;
phase = 2*`M_PI*idtmod(fsin, 0.0, 1.0, -0.5); t_delay = va*sin(phase); end end
V(out) <+ transition(vout,t_delay,t_tran); end
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