Andrew Beckett
Senior Fellow
Offline
Life, don't talk to me about Life...
Posts: 1742
Bracknell, UK
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You can't use SystemVerilog with Spectre (similarly you can't use Verilog, VHDL, or Verilog-AMS with spectre either, since it requires an event-driven simulator). You can use SystemVerilog with AMS Designer though since that's a mixed-signal simulator, and really there's nothing special you need to do for this. If using ADE, you'd create SystemVerilog textual views, or you can reference external files with a .sv suffix - it just works.
Regards,
Andrew.
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