edstrom
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Hi,
I am struggling with modelling a current source in verilogAMS. An ideal current source with a load would be
I(vdd, ibias) <+ 20e-6; for a current pin ibias. The problem with convergence comes with this implementation when the pin ibias is unloaded. The simulator will drive that current without any load, resulting in a very large voltage, resulting in a zero diagonal unsolvable matrix.
What would be necessary, is to model the output impedance properly. I have tried to short the output through a large resistor.
V(ibias,vss) <+I(ibias,vss)*100e6;
But the above statement still drives the current to the output ibias, generating convergence issues.
What would be the proper way to model this?
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