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Mar 29th, 2020, 11:45am
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Power Supply Induced Jitter for oscillator with multiple dividers (Read 61 times)
Anish
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Power Supply Induced Jitter for oscillator with multiple dividers
Feb 13th, 2020, 11:13am
 
Hello,
I am simulating an LC oscillator that drives a CMOS div4 and div5. I am interested in the Power Supply induced jitter at the output of the LC oscillator. To achieve this, I do the following-
1) Run PSS in oscillator mode with a beat frequency of LC_freq/20. I point to the oscillator output as the oscillator nodes.
2) Run Sampled PAC and find the voltage gain from my supply to the output of the LC (vgain).
3) Find the slope of my waveform from pss_td (slope) and use vgain/slope as the jitter induced by 1V movement on supply.

I have the following questions-
1) I know that I am supposed to point to the divider output as the oscillating node for PSS and specify that as the beat frequency. But since I have two dividers, which one do I pick? and what should the beat frequency be?
With lc_freq/20 as beat frequency and lc output as oscillating node, I see convergence issues as tstab tran is choosing lc_freq/36 (?) as fundamental. If I pick lc_freq/10 as beat frequency and lc output as oscillating node, some corners converge while others pick lc_freq/4 as fundamental.

2) Is the method I use for finding Power Supply induced jitter correct?

Thanks,
Anish
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Ken Kundert
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Re: Power Supply Induced Jitter for oscillator with multiple dividers
Reply #1 - Mar 23rd, 2020, 2:19pm
 
Why do you include the dividers? You can make this a faster and more robust simulation by only simulating the oscillator.

What you select as the oscillators nodes is not critical. They should just have a large signal present. Generally we specify a nodes that contain a clean signal at the fundamental frequency, but I don't think it matters that much as long as you converge.

The 'beat frequency' is a misnomer. It is mislabelled.  What is should say is 'fundamental frequency'. The fundamental frequency is the highest frequency that divides evenly into all non-zero signal components. In other words, all signal components presents should be  harmonics of the fundamental frequency. Yet another way of saying it is that all signal components should be a frequencies that are integer multiples of your fundamental frequency.

In your circuit, the fundamental frequency is the oscillator frequency divided by 20.

The approach you are taking looks okay to me, though I would get rid of the dividers and focus only on the oscillator.

-Ken
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Anish
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Re: Power Supply Induced Jitter for oscillator with multiple dividers
Reply #2 - Mar 23rd, 2020, 2:33pm
 
Thanks for you response, Ken.
The reason I have the dividers is that the divider capacitive load gets modulated by the power supply noise and modulates the frequency of the LC oscillator.
I solved the convergence issues by cascading a div4 with my div5 to actually generate a div20 in my schematic. Of course, this is less than ideal but I found this to be the quickest way.
Thanks again,
Anish
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