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Trade-off between LDO max Iout AND PSRR (Read 722 times)
blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #15 - May 20th, 2020, 2:36am
 
Quote:
Are you aware that your output transistor is 48.000/0.18 um= 48 mm / 0.18 um = 4.8 cm / 0.18 um ?


ok, but if I do not use such large output mosfet M20, this 3A LDO will have bad transient response performance.

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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #16 - May 20th, 2020, 3:02am
 
1. Change Vin to VDD (Vdd) or VDA (Vda) or any that indicates that it is power supply not the input voltage as usual to the input differential pair.

2. Do you really want to simulate power supply noise as 3.3 V +/- 1.0 V? Are you aware that usually voltage tolerance of CMOS transistors in analog CMOS IC design is power supply +/- 10%. That is, for 3.3 V it is 3.63 V max. In normal conditions your circuit would be dead.
Moreover, if you want to apply 2.3 V as power supply you should simulate whether the opamp works with such low voltage properly (e.g. AC characteristic, so on).


What I would recommend you is to move to the basic architecture and then modify it step by step. You have a typical problem that you took too complicated architecture, you haven't simulated it  for opamp parameters and you do not control it. You try to change and you do not know what may be the effects. Really, it is a good idea to move to an easier architecture. You will be able to control it and understand how PSRR affects it.
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #17 - May 20th, 2020, 6:35am
 
Combining your advices 1 and 2 in your previous post above, I have the following circuit without compromising performance for both transient response and AC response. However, PSRR still stay the same at 40dB.

If I increase width (m) of M7 and M8 to 80 as suggested here, then PSRR improves to 50dB.



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« Last Edit: May 20th, 2020, 10:02am by blue111 »  
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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #18 - May 21st, 2020, 1:24am
 
blue111 wrote on May 20th, 2020, 6:35am:
Combining your advices 1 and 2 in your previous post above, I have the following circuit without compromising performance for both transient response and AC response.

I would like to help you, but I see I won't be able XD.
What exactly have you changed? What I see:
- CSR block is returned ...
- power supply is 5V ...
- M20 is 4.000 um / 0.18 um = 4 mm / 0.18 um

Really you should do step by step. CSR should be deleted.

What should be the proper power supply for transistor models that you use? Check it. You chose models so you should know what power supply they work with.



blue111 wrote on May 20th, 2020, 6:35am:
without compromising performance for both transient response and AC response.

Not surprising. Now you have more voltage room in transient simulation. Previously your power supply was 3.3 +/- 1V. Now 5V +/- 0.5V.


blue111 wrote on May 20th, 2020, 6:35am:
However, PSRR still stay the same at 40dB.

Not surprising. AC simulations does not care about power supply value. What it cares are operation points and small signal models.


blue111 wrote on May 20th, 2020, 6:35am:
If I increase width (m) of M7 and M8 to 80 as suggested here, then PSRR improves to 50dB.

That's interesting. That would mean that there is a cause in your first stage what I expected and asked you to check the output of the first stage.

Ok, do what you want. Either shoot with many random changes or have patience and do step by step. Your choice.
For sure what I can recommend you should learn, read more about opamps. There are many resources in the internet.
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« Last Edit: May 22nd, 2020, 1:11am by Tako »  
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #19 - May 22nd, 2020, 3:22am
 
See https://github.com/promach/LDO/tree/development for the latest circuit.
Ignore the pictures inside README because they do not reflect the current circuit.

PSRR =70dB by increasing gain of the differential error amplifier stage
All other performance metrics results remain unchanged.



Now, I am left with 2 other issues.

1. Transient Response : Sudden increase or decrease in output load current
2. Phase margin plot looks strange....






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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #20 - May 22nd, 2020, 7:47am
 
blue111 wrote on May 22nd, 2020, 3:22am:
See https://github.com/promach/LDO/tree/development for the latest circuit.
Ignore the pictures inside README because they do not reflect the current circuit.

Ok, thanks.


blue111 wrote on May 22nd, 2020, 3:22am:
PSRR =70dB by increasing gain of the differential error amplifier stage
All other performance metrics results remain unchanged.

What exactly is "increasing gain of the differential error amplifier stage"? What I see you changed M7 and M8. What you did is: INCREASING THE LENGTH. Something that I told you before. One of two common techniques to fight with PSRR.
Come on blue111 ...


blue111 wrote on May 22nd, 2020, 3:22am:
1. Transient Response : Sudden increase or decrease in output load current

What exactly is your problem? What would you like to achieve? Do you expect to have a perfect straight line on the level of 2V for 3A output current changes?


blue111 wrote on May 22nd, 2020, 3:22am:
2. Phase margin plot looks strange....

Depends. Rather further decrease of phase is expected but it may just be the problem of the simulator. Transient simulation look fine. What you can do is to test for abrupt differential pair input voltage changes:

- see attached file "step response.png" (source https://payhip.com/b/5Srt, paid version)
- https://en.wikipedia.org/wiki/Step_response
- Camenzind http://www.designinganalogchips.com (I do not remember which page exactly, but he writes about simulator's problem with phase during simulations and about step response test)
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step_response_002.png
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #21 - May 22nd, 2020, 8:40am
 
The following bode plot is without CLoad.

Note that gain never reaches 0dB ......

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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #22 - May 24th, 2020, 8:17am
 
Even with 1us rise time and 1us fall time on Iout, the voltage overshoot and undershoot for Vout is still very serious

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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #23 - May 25th, 2020, 1:20am
 
Now you changed something further in the circuit as now even the phase drops only by 90 degrees not 180. Try to compensate or verify whether you do a proper AC characteristic test.

In reality, it will be hard for LDO to work with a "beautiful" sinusoidal power supply 5V +/- 0.5V and to work without external capacitor.
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #24 - May 26th, 2020, 4:19am
 
Why would the AC gain never reach 0dB ?

Which circuit node introduces the zero near 1MHz ?
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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #25 - May 27th, 2020, 1:17am
 
I would propose to make a standard AC characteristic test as I wrote you and see whether the results are the same.

What is M14 for?
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #26 - May 27th, 2020, 8:55pm
 
Quote:
standard AC characteristic test


Which standard AC test ? I am pretty sure that my current test setup presents some problem.

Quote:
What is M14 for?


It is for active elimination of RHPZ of miller compensation.





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Tako
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Re: Trade-off between LDO max Iout AND PSRR
Reply #27 - May 30th, 2020, 3:23am
 
blue111 wrote on May 27th, 2020, 8:55pm:
It is for active elimination of RHPZ of miller compensation.

I see. I haven't seen it for a long time and did not recognize it.



blue111 wrote on May 27th, 2020, 8:55pm:
Which standard AC test ? I am pretty sure that my current test setup presents some problem.

I am also suspicious about your AC testbench. Maybe you wrote it, but for AC testbench you use a single voltage source in the feedback loop as suggested on YouTube of LTSpice tutorial. Long time ago I tried to set such testbench and I remember I had problems. I do not remember what those problems were exactly.
I would propose the old, known AC testbench, that is, breaking the loop and inserting capacitor and resistor/inductor. See attached picture from https://payhip.com/b/5Srt ("Preview" in top right corner).

[ https://payhip.com/b/5Srt - "Preview" in top right corner]
"The easiest way to obtain the AC characteristic is to
break the loop using a large inductor and to connect a large capacitor to the negative input as
presented in Fig. 1.24:

The large inductor behaves as a very big resistance for AC signals. The large capacitor
keeps the bias on the negative input and ensures that any AC signal that leaks through the
inductor is shorted to the ground.
Some simulators enable to use a resistor instead of the inductor. In such case, a designer
specifies one resistance value that is seen in AC simulation and another one for all the other
simulations. The advantage of this solution over the inductor usage is the fact that the inductor
represents a different “resistance” value (electrical reactance to be specific) for different
frequencies. The higher the frequency, the higher the inductor's reactance. Hence, the inductor
is more leaky for lower frequencies and the AC characteristic may look a little bit strange
when very low frequencies are desired to be observed. On the contrary, the resistor keeps only
one resistance value across all frequency range."


Last remark: I see that you try to compensate your opamp using two paths: M14 and M22. Is that intentional?
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ac_test.png
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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #28 - May 30th, 2020, 3:55am
 
See the result using the known AC testbench setup





If I remove only C2 (removing C1 does not have observable effect) from the circuit, then see the following result :

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blue111
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Re: Trade-off between LDO max Iout AND PSRR
Reply #29 - Jun 3rd, 2020, 9:45am
 
I have updated the AC test setup at https://github.com/promach/LDO/blob/development/LDO_gain_phase_margin.asc

1) The phase margin performs really bad when the output load capacitor CL is removed. Any advice ?

2) Why would length L of M7, M8, M11, M17 affect the load transient response ? As L increases, the Vout overshoot and undershoot gets worse.

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