The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jul 13th, 2020, 7:35pm
Pages: 1 2 3 
Send Topic Print
Trade-off between LDO max Iout AND PSRR (Read 741 times)
Tako
Community Member
***
Offline



Posts: 83

Re: Trade-off between LDO max Iout AND PSRR
Reply #30 - Jun 05th, 2020, 3:36am
 
Great work with AC characteristic standard test. Now the situation has more light. It looks like you have a problem with compensation. That is, your circuit is not compensated in right way. Do you try to compensate your circuit using C1 and C2?
Another problem may be that you try to make a perfect circuit. As I understood, initially, you wanted your LDO to have high phase margin, no output overshoots, work for high power supply swing etc. In analog CMOS design the key word is: tradeoff.

The another problem is that normally LDO has big output capacitor. It is so big that no compensation is required as the output capacitor introduces pole that is enough to compensate the LDO properly:

[https://payhip.com/b/5Srt - paid version]
"Very often the voltage regulator works with big capacitances, for example 10 pF or
more, as presented in Fig. 5.5. That can be the case when it is used to create a power supply
voltage on a chip for a specific group of blocks. For example, the voltage regulator may be
used in a batteryless RF chip to provide the digital power supply voltage Vdigital (or VDDD
comparing to VDDA). Such chip takes the energy from the RF field. Once, the analog power
supply VDDA is up, the digital power supply VDDD may be created. The input voltage of the
regulator, a voltage reference, may be that of the bangap, that is 1.2 V and the regulator may
provide stable 1.8 V for the digital portion of the chip. The big capacitor at the output, called a
bypass capacitor, is needed for abrupt big currents taken by the digital circuits as they use
power only when changing states (between states no or minimal current is taken).

Usually, the Miller compensation is used to achieve the proper phase margin. Hence, the
usage of the compensation capacitor Cc and zero-nulling resistor Rz. The presented
architecture has two poles: one at the gate of M6 and the second at the opamp output. The
former is moved down in the frequency due to the Miller phenomenon, when using the
compensation capacitor Cc. However, when the big capacitance is connected to the opamp
output, it may happen that to achieve the proper phase margin, it is easier to make the output
capacitance even bigger. Due to the big load capacitance, the output pole has moved down in
the frequency so much that it is a dominant pole now and the compensation capacitor Cc
should be connected between the output and the ground terminals to achieve the desired phase
margin. Consider the regulator architecture presented in Fig. 5.7. Here, only Cload capacitor is
used to achieve the proper phase margin (Cload is the sum of the load and the compensation
capacitances). Transistor M7 from Fig. 5.6 has been deleted to save power and to remove unnecessary current branch as Cload capacitor is needed to be charged only. Sometimes, there
may be a need to make M6 big to allow the regulator supplying significant amounts of the
output current."
Back to top
 
 
View Profile   IP Logged
Tako
Community Member
***
Offline



Posts: 83

Re: Trade-off between LDO max Iout AND PSRR
Reply #31 - Jun 5th, 2020, 3:40am
 
blue111 wrote on Jun 3rd, 2020, 9:45am:
1) The phase margin performs really bad when the output load capacitor CL is removed. Any advice ?

See the answer about the output capacitor in the previous post.



blue111 wrote on Jun 3rd, 2020, 9:45am:
2) Why would length L of M7, M8, M11, M17 affect the load transient response ? As L increases, the Vout overshoot and undershoot gets worse.

L longer in the signal path = slower the circuit
Back to top
 
 
View Profile   IP Logged
blue111
Community Member
***
Offline



Posts: 71

Re: Trade-off between LDO max Iout AND PSRR
Reply #32 - Jun 5th, 2020, 5:08am
 
I did not see any Figures 5.5 , 5.6 and 5.7

Could you reupload those figures ?

By the way, do I need "AC 1" for Vref ?

If I remove "AC 1" , then the bode plot goes horribly wrong, becoming strange unrecognizable shape

Back to top
 
 
View Profile   IP Logged
blue111
Community Member
***
Offline



Posts: 71

Re: Trade-off between LDO max Iout AND PSRR
Reply #33 - Jun 12th, 2020, 2:56am
 
Back to top
 
 
View Profile   IP Logged
Tako
Community Member
***
Offline



Posts: 83

Re: Trade-off between LDO max Iout AND PSRR
Reply #34 - Jul 2nd, 2020, 4:07am
 
blue111 wrote on Jun 5th, 2020, 5:08am:
By the way, do I need "AC 1" for Vref ?

If I remove "AC 1" , then the bode plot goes horribly wrong, becoming strange unrecognizable shape


Sure. AC characteristic test should be performed when opamp is properly biased.
Back to top
 
 
View Profile   IP Logged
blue111
Community Member
***
Offline



Posts: 71

Re: Trade-off between LDO max Iout AND PSRR
Reply #35 - Jul 2nd, 2020, 4:28am
 
I am now using Middlebrook's Method to measure phase margin.

WHY if I remove Cout and change values of m of both M12 and M16 to m=8 , then it gives good phase margin (phase plot starts at 180 degree (negative feedback) and decreases monotonously. When it crosses the 0 degree with magnitude >= 0 dB, the feedback circuit is unstable according to Bode stability criterion.) ?

WHY doing so will result in a trade-off of a much larger load regulation spike (800mV) in Vout ?
Back to top
 
 
View Profile   IP Logged
Tako
Community Member
***
Offline



Posts: 83

Re: Trade-off between LDO max Iout AND PSRR
Reply #36 - Jul 2nd, 2020, 4:51am
 
blue111 wrote on Jul 2nd, 2020, 4:28am:
WHY if I remove Cout and change values of m of both M12 and M16 to m=8 , then it gives good phase margin (phase plot starts at 180 degree (negative feedback) and decreases monotonously. When it crosses the 0 degree with magnitude >= 0 dB, the feedback circuit is unstable according to Bode stability criterion.) ?

Because Cout should be rather expected to be one of the main poles.



blue111 wrote on Jul 2nd, 2020, 4:28am:
WHY doing so will result in a trade-off of a much larger load regulation spike (800mV) in Vout ?

Because, now there is no big capacitance at the output, so the output voltage may rise faster and hence the spikes.
Back to top
 
 
View Profile   IP Logged
blue111
Community Member
***
Offline



Posts: 71

Re: Trade-off between LDO max Iout AND PSRR
Reply #37 - Jul 2nd, 2020, 5:17am
 
I am asking about "changing m of both M12 and M16 to m=8"
Back to top
 
 
View Profile   IP Logged
Pages: 1 2 3 
Send Topic Print
Copyright 2002-2020 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.