vivkr
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Hello All,
I would like to understand the behavior of parasitic resistors in vertical PNP devices manufactured in the leading-edge CMOS processes.
The key parasitics are emitter and base (including base spreading) resistances. The device model provided by the foundry has lumped both these into 1 single term, namely, the emitter resistance and set this to a constant number.
Given that the precision of my circuits is primarily limited by these, I would like to understand if they are truly relatively constant (say within +/- 20%) over process and temperature or if they vary wildly (say +/- 100% or so). If the former, then I could design for the nominal values of these parameters and be done. If the latter, then much more expensive multi-point calibration would be needed, which would be prohibitive.
Of course, one could get around the issues by biasing the devices at very low current densities (say 1/10th of what I am using), but that would make for a very inefficient design.
Thanks for your hints and comments.
Vivek
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