This book was written in 2004 - when parasitics were by several orders of magnitude less important than now (in 2020 - at 7nm, 5nm nodes).

Parasitic extraction is done not on architecture, but on the layout.

It's very hard to decouple parasitics at the block level with parasitics at the higher hierarchy level, as there may be a lot of interaction between these two levels - both resistive interaction (where metals at the lower hierarchy level are used for top-level routing - for example, power nets), and capacitive coupling.

As an example, many IR/EM effects and problems can be happening at the top hierarchy level - that is finished late in the deign process, and the size becomes too big even for industry standard, sign-off level IR/EM tools to handle it.

I am not an expert in functional verification.

I have looked through that paper, and some statements there, may have been true in 2007, are wrong in the year 2020, when you are dealing with FinFET technologies (16nm and lower nodes).

For example, this: "Near the end of the design, the transistor level representation can also include the parasitics."

The difference in circuit behavior for schematic simulation and for post-layout simulation is so huge, that pre-layout simulations are meaningless, and are not used any more.
That's because of the huge impact of parasitics - on everything - IR drop, signal delay, matching, etc.

Also, is you verify your blocks then combine several blocks together - they may behave differently, because of the global IR drop effects, or clock, etc.

You do need to verify at the top hierarchy level.
But doing a straightforward post-layout SPICE simulation is simply impossible, because of the huge size of the system.

Even doing IR/EM analysis at the top level is nearly impossible, using standard IR/EM tools - because they have to be sign-off, i.e. accurate, and use SPICE for current sources calculation.