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May 23rd, 2022, 10:50pm
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 Linear Voltage Buffer (Read 682 times)
 Cascody New Member Offline Posts: 4 Allahabad Linear Voltage Buffer Dec 14th, 2020, 7:54am   I have to design a linear voltage buffer in 65nm technology with the following specifications:BW: 10-20MHzInput Voltage Range: 0 to 0.9VTHD: <-80 dBInput source is a charge pump ramp generator (10MHz) with output resistance= 2.2k and cap=1.4pF. The buffer has to drive a capacitor of 400pF. I have tried the bootstrapped cascode source follower topology with cascode current source. Its THD is -65dB only. Please suggest a suitable topology for the buffer. Back to top IP Logged
 dnw Junior Member Offline Posts: 25 Re: Linear Voltage Buffer Reply #1 - Dec 19th, 2020, 6:41am   I am guessing you are using pmos sf to shift up the signal.How big is the sf? I am guessing if the device is big there might be distortion at the input.Or is it limited by the current source or sf?Also I am assuming main sf you have is having bulk and short connected. Back to top IP Logged
 Cascody New Member Offline Posts: 4 Allahabad Re: Linear Voltage Buffer Reply #2 - Dec 19th, 2020, 11:29am   I am using the attached buffer circuit. PMOS-NMOS stages are used to keep the output voltage within the desired range (<1.2 V). The main PMOS SF device is 4u/60n, and NMOS SF device is 40u/60n. Bulk and source are short. I'm getting similar distortion even with single-stage PMOS SF buffer. Back to top IP Logged
 dnw Junior Member Offline Posts: 25 Re: Linear Voltage Buffer Reply #3 - Dec 19th, 2020, 2:30pm   Not 100% sure but speculating it could be gds of 60n pmos sfDO you see the same result if you replace the pmos current source with ideal current source? If you still see similar results does increasing the length of pmos sf helps.Also how much nonlinearity you measure at the input of pmos sf itself? Back to top IP Logged
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