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Nov 30th, 2021, 7:20am
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how to set initial state of digital circuit in AMS simulation? (Read 20 times)
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how to set initial state of digital circuit in AMS simulation?
Nov 19th, 2021, 12:27am
 
I am using cadence AMS to do mixed signal simulation(analog circuit + digital circuit(verilog.v)), in digital cicuit, some DFFs used in frequency divider do not have initial reg value, the reg initial value should be set to avoid X state.
Would someone teach me how to set all regs' initial value to 0 or 1?

Many thanks.
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