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Dec 9th, 2022, 8:55am
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Assignment timing defined by timer event (Read 128 times)
sjwprc
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Assignment timing defined by timer event
Aug 07th, 2022, 3:06am
 
In the verilogA, i define a integer N, which is set to 0 at 25ms by timer(25), in the transient, i notice the waveform is shown as attachment. There is obvious drop procedure. Although N = 0 at 25ms, but it starts to drop from ~ 24.5ms, is there anyway to avoid such behavior?
I have tried to use different errpreset, it can be improved by conservative, but still not good enough.
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Ken Kundert
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Re: Assignment timing defined by timer event
Reply #1 - Aug 9th, 2022, 10:54pm
 
If you want help, you should give the model.
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Ken Kundert
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Re: Assignment timing defined by timer event
Reply #2 - Aug 10th, 2022, 8:00pm
 
I recommend you read Functional Modeling.  It explains many of the things you must do to get an accurate, robust, and efficient abstract model of a circuit.

-Ken
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