Yutao Liu wrote on Apr 26th, 2009, 8:26pm:And I change the testbench a little (as shown below), and the result seems more reasonable.
Is my testbench feasible to simulate what I want?
What on earth do you want to do ? How is your result reasonable ? Instance "G0" which is VCCS has no meaning at all because control voltage of "G0" is always zero.
And both "I0" and "V3" also have no meaning at all.
Your circuit is no more than NMOS FET where Source is ground, Drain is 1.0V and Gate is opened.
Previously you said "I'm a student for analog/RF circuit design".
http://www.designers-guide.org/Forum/YaBB.pl?num=1235705814/6#6What on earth are you learning ?
Are you surely learning analog/RF circuit design ?
What you want to do is setting Gate voltage automatically to give target value as Source current at Vds=constant ?
If so, remove "I0" and replace "G0" with combinations of ideal OP-Amp, CCVS controled by current flowing through "V3" and reference voltage.
I think test bench which sheldon showed also can work for this purpose in case of MOSFET.
Maybe CCCS is used in this test bench.
http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-tran...However I think current monitor should be inserted to collector not emitter in case of BJT.
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i think the straightforward way is to connect source to ground, drain to a constant idc, put the drain voltage and a ref voltage to the inputs of an ideal opamp, connect the opamp output to the gate.