Yutao Liu wrote on Apr 30th, 2009, 1:46am:The simulation results exactly meet what i want.
I don't think so.
Apparently you were trying to flow Idrain=200uA without confirming Id-Vds characteristics of "n18" with L=0.35um and W=1.0um.
It is very common rule to confirm Id-Vds characteristics of DUT before forced biasing.
Warning you saw, "
Vgs has exceeded the oxide breakdown voltage" was quite natural result of your thoughtlessness.
If your trial was actual measurements, MOSFET might be broken.
Learn measurements using actual instruments. Not "EDA Tool Play".
A method which subgold suggested is unreasonable for low Vds region.
Compare results of (1) with results of (2) and (3).
(1) subgold suggestion(Id is forced, Vds is monitored)
(2) my suggestion(Vds is forced, Id is monitored)
(3) Bias condition searching using Optimizer of Agilent ADSsim(Vds is forced, Id is monitored)
Yutao Liu wrote on Apr 30th, 2009, 1:46am:But I don't quite understand why the opamp in ahdlLib is able to achieve the result while the vcvs in analogLib fails.
What 's the difference between them?
Maybe this is due to difference of behavior around in_p-in_n=0 between "analogLib/vcvs" and "ahdlLib/opamp".
Yutao Liu wrote on May 1st, 2009, 7:05am:but discontinuity exist when vds is in low region, as shown below.
My schematic and the setting of the opamp is totally the same as you described above.
Do you have any idea what makes the discontinuity?
If you consider Id-Vds characteristics of "n18" with L=0.35um and W=1.0um,
this result is quite natural in condition of "Id is forced, Vds is monitored".
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