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Yutao Liu

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How to simulate this circuit in Spectre???
Apr 21^st, 2009, 6:56am

Hello everyone,

I want to observe gm of a nmos with a constant drain current but different vds.
The drain of nmos is connected with a current source and its source is connected to ground. How should I connect the gate of the nmos, when the drain current is constant but the vds is varying?

This circuit can be simulated in Hspice with a negative feedback, making use of amplifier, as descried in UC Berkeley EE240. However, the circuit can't work at Spectre due to problem of convergence.

Could anybody help?

Thanks!

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sheldon Community Fellow Offline Posts: 751	Re: How to simulate this circuit in Spectre??? Reply #1 - Apr 21^st, 2009, 7:41am Yutao, The testbench setup is discussed in the append http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-tran... The application is testing MOS transistor ft but the testbench can also be used for the application you are describing. Best Regards, Sheldon
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Yutao Liu Community Member Offline Posts: 76 Guangzhou, China	Re: How to simulate this circuit in Spectre??? Reply #2 - Apr 22^nd, 2009, 2:29am Thank you, sheldon. However, the picture in the website is not clear. could you send me a netlist of that testbench? Thanks a lot!
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Yutao Liu

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Re: How to simulate this circuit in Spectre???
Reply #3 - Apr 26^th, 2009, 8:26pm

sheldon wrote on Apr 21^st, 2009, 7:41am:

Yutao,

� The testbench setup is discussed in the append

http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-tran...

The application is testing MOS transistor ft but the testbench can also
be used for the application you are describing.

�Best Regards,

� � Sheldon

hi, Sheldon.
I have tried the testbench you recommended, however the result seems inconsistent with prediction. And I found that the drain current of the MOSFET did change when sweeping vds, which seems deviate my requirement obviously.Did you try that testbench? Why the drain current would change?

And I change the testbench a little (as shown below), and the result seems more reasonable. Is my testbench feasible to simulate what I want?
What's your opinion?
Thanks!

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scheme_001.PNG

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pancho_hideboo

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Re: How to simulate this circuit in Spectre???
Reply #4 - Apr 27^th, 2009, 3:35am

Yutao Liu wrote on Apr 26^th, 2009, 8:26pm:

And I change the testbench a little (as shown below), and the result seems more reasonable.
Is my testbench feasible to simulate what I want?

What on earth do you want to do ? Undecided

How is your result reasonable ? Kiss

Instance "G0" which is VCCS has no meaning at all because control voltage of "G0" is always zero.
And both "I0" and "V3" also have no meaning at all.
Your circuit is no more than NMOS FET where Source is ground, Drain is 1.0V and Gate is opened.

Previously you said "I'm a student for analog/RF circuit design". Cheesy

http://www.designers-guide.org/Forum/YaBB.pl?num=1235705814/6#6

What on earth are you learning ?
Are you surely learning analog/RF circuit design ? Huh

What you want to do is setting Gate voltage automatically to give target value as Source current at Vds=constant ?
If so, remove "I0" and replace "G0" with combinations of ideal OP-Amp, CCVS controled by current flowing through "V3" and reference voltage.

I think test bench which sheldon showed also can work for this purpose.
Maybe CCCS is used in this test bench.
http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-tran...
However I think current monitor should be inserted to drain(collector) not source(emitter).

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« Last Edit: Apr 27^th, 2009, 3:11pm by pancho_hideboo »

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subgold

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Re: How to simulate this circuit in Spectre???
Reply #5 - Apr 27^th, 2009, 1:38pm

pancho_hideboo wrote on Apr 27^th, 2009, 3:35am:

Yutao Liu wrote on Apr 26^th, 2009, 8:26pm:

And I change the testbench a little (as shown below), and the result seems more reasonable.
Is my testbench feasible to simulate what I want?

What on earth do you want to do ? Undecided

How is your result reasonable ? Kiss

Instance "G0" which is VCCS has no meaning at all because control voltage of "G0" is always zero.
And both "I0" and "V3" also have no meaning at all.
Your circuit is no more than NMOS FET where Source is ground, Drain is 1.0V and Gate is opened.

Previously you said "I'm a student for analog/RF circuit design". Cheesy

http://www.designers-guide.org/Forum/YaBB.pl?num=1235705814/6#6

What on earth are you learning ?
Are you surely learning analog/RF circuit design ? Huh

What you want to do is setting Gate voltage automatically to give target value as Source current at Vds=constant ?
If so, remove "I0" and replace "G0" with combinations of ideal OP-Amp, CCVS controled by current flowing through "V3" and reference voltage.

I think test bench which sheldon showed also can work for this purpose in case of MOSFET.
Maybe CCCS is used in this test bench.
http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-tran...
However I think current monitor should be inserted to collector not emitter in case of BJT.

i think what yutao wants is not setting Gate voltage automatically to give target value as Source current at Vds=constant , but setting Vds to automatically give target Vgs at Ids=constant .

i think the straightforward way is to connect source to ground, drain to a constant idc, put the drain voltage and a ref voltage to the inputs of an ideal opamp, connect the opamp output to the gate.

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Yutao Liu

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Re: How to simulate this circuit in Spectre???
Reply #6 - Apr 27^th, 2009, 6:56pm

subgold wrote on Apr 27^th, 2009, 1:38pm:

pancho_hideboo wrote on Apr 27^th, 2009, 3:35am:

Yutao Liu wrote on Apr 26^th, 2009, 8:26pm:

And I change the testbench a little (as shown below), and the result seems more reasonable.
Is my testbench feasible to simulate what I want?

What on earth do you want to do ? Undecided

How is your result reasonable ? Kiss

Instance "G0" which is VCCS has no meaning at all because control voltage of "G0" is always zero.
And both "I0" and "V3" also have no meaning at all.
Your circuit is no more than NMOS FET where Source is ground, Drain is 1.0V and Gate is opened.

Previously you said "I'm a student for analog/RF circuit design". Cheesy

http://www.designers-guide.org/Forum/YaBB.pl?num=1235705814/6#6

What on earth are you learning ?
Are you surely learning analog/RF circuit design ? Huh

What you want to do is setting Gate voltage automatically to give target value as Source current at Vds=constant ?
If so, remove "I0" and replace "G0" with combinations of ideal OP-Amp, CCVS controled by current flowing through "V3" and reference voltage.

I think test bench which sheldon showed also can work for this purpose in case of MOSFET.
Maybe CCCS is used in this test bench.
http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-tran...
However I think current monitor should be inserted to collector not emitter in case of BJT.

i think what yutao wants is not setting Gate voltage automatically to give target value as Source current at Vds=constant , but setting Vds to automatically give target Vgs at Ids=constant .

i think the straightforward way is to connect source to ground, drain to a constant idc, put the drain voltage and a ref voltage to the inputs of an ideal opamp, connect the opamp output to the gate.

Thanks for your reply!
I am really a student studying analog/RF design, although I am not so familiar with analog design as you.

What subgold said above is what i want to obtain.
I want to use gm/Id methodology to design my circuit. And according to the notes from EE240 UC berkeley, I have to choose a appropriate channel length of MOS for a given gain first. So, I want to know the intrinsic gain(gm*ro) of MOS with different channel length when sweeping vds under a constant Ids.
I had tried the method mentioned by subgold in Spectre for several times, and I used VCVS as the ideal opamp, with the gain of 100. However, the simulator warned that Vgs and Vds exceeded the breakdown voltage, and the simulation result shown below. Is the gain of the ideal opamp set too high? Or is there any mistakes I have made?

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scheme_002.PNG

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pancho_hideboo

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Re: How to simulate this circuit in Spectre???
Reply #7 - Apr 27^th, 2009, 9:43pm

Yutao Liu wrote on Apr 27^th, 2009, 6:56pm:

I am really a student studying analog/RF design, although I am not so familiar with analog design as you.

Study hard. Grin

Yutao Liu wrote on Apr 27^th, 2009, 6:56pm:

I want to know the intrinsic gain(gm*ro) of MOS with different channel length when sweeping vds under a constant Ids.

Testbench which sheldon showed, my suggestion and subgold suggestion are all valid for your purpose.

You don't seem to understand DC characteristics of MOSFET.
Drain current of MOSFET, Ids is dependent on both Vgs and Vds. So Ids=Ids(Vgs, Vds).

What you want to do is setting gate bias Vgs automatically for swept Vds under keeping Ids as constant value.　

Testbench which sheldon showed is attractive because it doesn't require ideal-opamp.

Yutao Liu wrote on Apr 27^th, 2009, 6:56pm:

I had tried the method mentioned by subgold in Spectre for several times, and I used VCVS as the ideal opamp.

Use "ahdllib/opamp with gain=100dB" instead of "analogLib/vcvs".

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« Last Edit: Apr 28^th, 2009, 12:13am by pancho_hideboo »

Kita━━━━━━(ﾟ∀ﾟ)━━━━━━ !!!!!
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http://www.youtube.com/watch?v=mjIxGh55bMM&feature=related

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subgold

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Re: How to simulate this circuit in Spectre???
Reply #8 - Apr 28^th, 2009, 3:01am

Yutao Liu wrote on Apr 27^th, 2009, 6:56pm:

subgold wrote on Apr 27^th, 2009, 1:38pm:

pancho_hideboo wrote on Apr 27^th, 2009, 3:35am:

Yutao Liu wrote on Apr 26^th, 2009, 8:26pm:

And I change the testbench a little (as shown below), and the result seems more reasonable.
Is my testbench feasible to simulate what I want?

What on earth do you want to do ? Undecided

How is your result reasonable ? Kiss

Instance "G0" which is VCCS has no meaning at all because control voltage of "G0" is always zero.
And both "I0" and "V3" also have no meaning at all.
Your circuit is no more than NMOS FET where Source is ground, Drain is 1.0V and Gate is opened.

Previously you said "I'm a student for analog/RF circuit design". Cheesy

http://www.designers-guide.org/Forum/YaBB.pl?num=1235705814/6#6

What on earth are you learning ?
Are you surely learning analog/RF circuit design ? Huh

What you want to do is setting Gate voltage automatically to give target value as Source current at Vds=constant ?
If so, remove "I0" and replace "G0" with combinations of ideal OP-Amp, CCVS controled by current flowing through "V3" and reference voltage.

I think test bench which sheldon showed also can work for this purpose in case of MOSFET.
Maybe CCCS is used in this test bench.
http://www.cadence.com/Community/blogs/rf/archive/2008/08/09/simulating-mos-tran...
However I think current monitor should be inserted to collector not emitter in case of BJT.

i think what yutao wants is not setting Gate voltage automatically to give target value as Source current at Vds=constant , but setting Vds to automatically give target Vgs at Ids=constant .

i think the straightforward way is to connect source to ground, drain to a constant idc, put the drain voltage and a ref voltage to the inputs of an ideal opamp, connect the opamp output to the gate.

Thanks for your reply!
I am really a student studying analog/RF design, although I am not so familiar with analog design as you.

What subgold said above is what i want to obtain.
I want to use gm/Id methodology to design my circuit. And according to the notes from EE240 UC berkeley, I have to choose a appropriate channel length of MOS for a given gain first. So, I want to know the intrinsic gain(gm*ro) of MOS with different channel length when sweeping vds under a constant Ids.
I had tried the method mentioned by subgold in Spectre for several times, and I used VCVS as the ideal opamp, with the gain of 100. However, the simulator warned that Vgs and Vds exceeded the breakdown voltage, and the simulation result shown below. Is the gain of the ideal opamp set too high? Or is there any mistakes I have made?

somehow i didn't notice sheldon's post at the first place, now i see it, and i agree with pancho_hideboo that it is quite simple and nice. you may also try that out.

anyway, i dont see why the bench using opamp feedback fails. 100 gain is not high at all (or did you mean 100db?) please post ur schematic and result waveforms (not only the gm curve you posted) so that others can check if there is any mistake.

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Yutao Liu

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Re: How to simulate this circuit in Spectre???
Reply #9 - Apr 28^th, 2009, 7:08am

subgold wrote on Apr 28^th, 2009, 3:01am:

somehow i didn't notice sheldon's post at the first place, now i see it, and i agree with pancho_hideboo that it is quite simple and nice. you may also try that out.

Hi, subgold and �pancho_hideboo, thanks for your suggestion and patient.
Both of you really have taught me a lot.

I tried the testbench Sheldon introduced, both schematic and result waveforms are shown below. �I am sure that the schematic is totally the same as that in
http://www.cadence.com/Community/blogs/rf/archive/2008/07/16/measuring-transisto...
And I do the DC analysis with sweeping vds from 0 to 3.2 V, plotting the operation points as shown below.

However, I doubt the result because the drain current linearly increase in the range between 0 and 800pA, while I want the drain current keeps constant. Did I do something wrong during simulating?

Thank you so much!!!
Best regards!
Yutao

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scheme_003.PNG

« Last Edit: Apr 28^th, 2009, 8:03pm by Yutao Liu »

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pancho_hideboo

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Re: How to simulate this circuit in Spectre???
Reply #10 - Apr 28^th, 2009, 8:10am

Yutao Liu wrote on Apr 28^th, 2009, 7:08am:

And I do the DC analysis with sweeping vds from 0 to 3.2 V, plotting the operation points as shown below.

Show me your netlists with model file of "n18".

Show me Id-Vds characteristics of "n18" with L and W of your setting for various Vgs.
For example,
Vgs ; start=0.0, stop=0.8, step=0.1
Vds ; start=0.0, stop=3.2, step=0.01

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Kita━━━━━━(ﾟ∀ﾟ)━━━━━━ !!!!!
http://www7.plala.or.jp/ungeromeppa/flash/kita.html
http://www.youtube.com/watch?v=mjIxGh55bMM&feature=related

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Yutao Liu

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Re: How to simulate this circuit in Spectre???
Reply #11 - Apr 28^th, 2009, 7:25pm

pancho_hideboo wrote on Apr 28^th, 2009, 8:10am:

Yutao Liu wrote on Apr 28^th, 2009, 7:08am:

And I do the DC analysis with sweeping vds from 0 to 3.2 V, plotting the operation points as shown below.

Show me your netlists with model file of "n18".

Show me Id-Vds characteristics of "n18" with L and W of your setting for various Vgs.
For example,
Vgs ; start=0.0, stop=0.8, step=0.1
Vds ; start=0.0, stop=3.2, step=0.01

hi pancho_hideboo, following is the id-Vds characteristics of "n18".

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scheme_004.PNG

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pancho_hideboo Senior Fellow Offline Posts: 1424 Real Homeless	Re: How to simulate this circuit in Spectre??? Reply #12 - Apr 28^th, 2009, 7:52pm Yutao Liu wrote on Apr 28^th, 2009, 7:25pm: following is the id-Vds characteristics of "n18". I think it is impossible to get Ids=200uA with "n18" of your L and W. Increase W. Show me your netlists with model file of "n18".
Back to top	Kita━━━━━━(ﾟ∀ﾟ)━━━━━━ !!!!! http://www7.plala.or.jp/ungeromeppa/flash/kita.html http://www.youtube.com/watch?v=mjIxGh55bMM&feature=related IP Logged

Yutao Liu

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Re: How to simulate this circuit in Spectre???
Reply #13 - Apr 28^th, 2009, 8:24pm

pancho_hideboo wrote on Apr 28^th, 2009, 7:52pm:

Yutao Liu wrote on Apr 28^th, 2009, 7:25pm:

following is the id-Vds characteristics of "n18".

I think it is impossible to get Ids=200uA with "n18" of your L and W.
Increase W.

Show me your netlists with model file of "n18".

thank you so much, pancho_hideboo!
I also tried Ids=40uA and increase the W, but the Ids current still increases linearly.
attach is the netlists and the model of n18.
Thanks for your help again.

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netlist.rar

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pancho_hideboo

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Re: How to simulate this circuit in Spectre???
Reply #14 - Apr 28^th, 2009, 9:09pm

Yutao Liu wrote on Apr 28^th, 2009, 8:24pm:

attach is the netlists and the model of n18.

Both statements of parameter definition and statements of analysis don't exist. Angry

As I said to you repeatedly, no one except for you knows your specific situations.
What sizes on earth did you use as W and L for "n18" ? Angry

Show me complete netlists. e.g. "input.scs" if you use Cadence Spectre from ADE.

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