Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
timer for counting the number of http get request	Monte Kristo	1	1634	May 26^th, 2010, 4:44am By: Geoffrey_Coram
how to model the PSRR of a voltage reference	mowiehowie	2	2192	May 19^th, 2010, 7:27am By: Marq Kole
is possible to write model for piecewise linear source	seefree	6	10158	May 17^th, 2010, 4:11am By: Marq Kole
MATLAB to Cadence	e.fisher	10	8140	May 17^th, 2010, 2:47am By: e.fisher
model of filter	pdrobh	1	1601	May 14^th, 2010, 1:39am By: Marq Kole
$table_model funny results	mowiehowie	4	3517	May 14^th, 2010, 1:31am By: Marq Kole
verilog-ams variable in cadence calculator	Cri Azzolini	3	4146	May 14^th, 2010, 12:50am By: Marq Kole
verilogams simuation error	liletian	2	2026	May 12^th, 2010, 8:02am By: liletian
Multi-dimensional arrays in Verilog-AMS	mehregan	0	2621	May 7^th, 2010, 10:37am By: mehregan
Switching power	akhil	3	2469	May 7^th, 2010, 6:22am By: rajdeep
random number generation	rajdeep	1	2053	May 7^th, 2010, 4:28am By: rajdeep
Latch D->Latch T	Daniel Minan	1	1450	Apr 26^th, 2010, 6:28am By: boe
syntax?	colorcircle	1	1558	Apr 26^th, 2010, 4:41am By: Geoffrey_Coram
How to write a time amplifier?	5gougou	4	2989	Apr 22^nd, 2010, 12:23am By: 5gougou
code?	colorcircle	1	1520	Apr 21^st, 2010, 11:21pm By: Ken Kundert
Running average in Verilog-AMS	Cri Azzolini	4	7682	Apr 20^th, 2010, 4:17am By: Cri Azzolini
Probing port voltages of verilogA block from ams testbench	Dan Clement	6	4621	Apr 16^th, 2010, 5:52am By: Dan Clement
prefix adder	akhil	0	1138	Apr 15^th, 2010, 3:05am By: akhil
Verilog-A model for ADC	lyko	3	9770	Apr 14^th, 2010, 1:03am By: Marq Kole
Moved: QAM modulator - Started by: jdac_18 This Topic has been moved to Circuit Simulators by Ken Kundert

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