Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Running code depending on clock and time.	eddie	2	2113	Oct 9^th, 2009, 4:02am By: rajdeep
Phase noise to jittter in verilogA	nandy	1	2138	Oct 7^th, 2009, 7:38am By: ywguo
Do Verilog-A and Verilog-AMS solve analog processes differently?	engelbrl	3	3022	Oct 1^st, 2009, 9:17am By: Riad KACED
Simulators & Models	ktailor	3	2597	Sep 29^th, 2009, 10:46am By: Geoffrey_Coram
Verilog-A Syntax (head scratching dilema)	eddie	4	3338	Sep 22^nd, 2009, 8:42am By: eddie
Logical Behaviour for VerilogA	eddie	3	4166	Sep 17^th, 2009, 9:51am By: Geoffrey_Coram
discipline phase problem	bandpass	4	3975	Sep 14^th, 2009, 6:16am By: Geoffrey_Coram
case statement in verilog-A	rajdeep	4	13467	Aug 27^th, 2009, 6:07am By: rajdeep
Obtaining dynamic CPU time during Verilog execution	cmolsen	3	3510	Aug 25^th, 2009, 7:34am By: Andrew Beckett
Convergence Problem	Deb	3	3208	Aug 21^st, 2009, 3:45am By: rajdeep
laplace_nd()	flz	1	589	Aug 18^th, 2009, 7:55am By: Sumit Adhikari
Decimal to binary conversion	nishant22	3	1200	Aug 14^th, 2009, 7:20am By: boe
error	godfather	5	932	Aug 12^th, 2009, 2:33pm By: godfather
segmentation fault when I simulate a verlioga opamp model	hhd1983	4	3626	Aug 12^th, 2009, 2:25pm By: Andrew Beckett
vpi_get_analog_value() and t_vpi_analog_value - Verilog AMS LRM 2.3.1	Aspwy	1	1745	Aug 12^th, 2009, 1:37pm By: Andrew Beckett
convert rflib osc cell to VerilogA	Ian	1	1950	Jul 30^th, 2009, 5:18am By: Andrew Beckett
setup-time measurement	idriss	2	3138	Jul 15^th, 2009, 2:25am By: idriss
analysis type "static" not recognized	aaron_do	14	292	Jul 10^th, 2009, 7:05am By: Andrew Beckett
Is there a limitation for the vector size in Spectre?	couragebo	1	69	Jul 10^th, 2009, 7:02am By: Andrew Beckett
something about amsdirect	mikro	0	1054	Jul 10^th, 2009, 6:00am By: mikro

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