Designer’s Guide Community

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Subject	Started by	Replies	Views	Last post
Lambert-W function in verilog-A	337see733	2	738	Sep 26^th, 2007, 6:07pm By: 337see733
[q] transient noise in Verilog-A	Renekim	5	4765	Sep 26^th, 2007, 11:18am By: Ken Kundert
fatal internal errors	Eugene	3	3459	Sep 26^th, 2007, 8:40am By: Eugene
Syntax error while using genvar	magathi	1	2914	Sep 26^th, 2007, 1:49am By: Marq Kole
Accessing/Modifying "disciplines.vams"	Prathap	3	5348	Sep 25^th, 2007, 11:54pm By: Prathap
question about integral	James Bond	11	1615	Sep 25^th, 2007, 4:16am By: Geoffrey_Coram
How to implement induced gate noise current?	humble_student	4	3521	Sep 24^th, 2007, 9:35am By: Geoffrey_Coram
accuracy of absdelay()	Aigneryu	2	3701	Sep 17^th, 2007, 10:13am By: Aigneryu
delay model in verilog-a (ac response)	kanan	1	1823	Sep 13^th, 2007, 4:25am By: Geoffrey_Coram
Moved: Mentor ADVance MS - Started by: Forum Administrator This Topic has been moved to AMS Simulators by Forum Administrator.
Dynamic Array	Nano_Model	1	1873	Sep 12^th, 2007, 5:07am By: Geoffrey_Coram
battery model	grosser	8	9513	Sep 11^th, 2007, 6:13am By: Geoffrey_Coram
frequency	kamath	1	1873	Sep 10^th, 2007, 8:00am By: Geoffrey_Coram
verilog-A time delay model	dkumar	1	2609	Sep 6^th, 2007, 8:22am By: Jess Chen
syntax error about the comparator	James Bond	4	3073	Sep 3^rd, 2007, 10:43am By: James Bond
cross statement in example VCO in designers guide	sylak	1	1692	Aug 31^st, 2007, 8:23am By: Geoffrey_Coram
How to read a number from a file in Verilog-a?	jiji666666	0	1407	Aug 31^st, 2007, 5:49am By: jiji666666
Test bench design - tasks	jjrael	3	6712	Aug 27^th, 2007, 5:20am By: Geoffrey_Coram
passing parameters from verilog-a to ADE	just started	2	3084	Aug 23^rd, 2007, 8:08am By: just started
cap model	grosser	2	2206	Aug 23^rd, 2007, 7:23am By: grosser

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