wolf
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Hi Richard,
I'm facing the same problem. I think that this is due to the design kit and not to the bsim model. It depends if the channel resistance is implemented or not. If i run an ac sim and plot 1/impedance at the gate of the nmos in fct of frequency, it behaves like a pure capacitor, which means that the channel resistor is not implemented. Usually, vs=vd which means that the transistor is in the linear region. This situation is similar to a switch with Ron=1/(beta*(Vg-vt-vbulk) Except that this resistor is between drain and source instead of grid and bulk. However, for an approximation of the Q factor, this formula for the channel resistor should not be too far, what do you think?
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