analogben
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I am running a simple switched cap simulation that consists of an ideal switch, a series resistor, and a capacitor. I am using the veriloga sample-and-hold block provided on this website to sample the output, and I have allowed greater than 10 time constants to pass before performing any sampling or hold operation.
I would expect the noise density of this circuit to be consistent with having kT/C integrated over a bandwidth of 1/2 the sampling rate. I would also expect the circuit noise be independent of the series switch resistance.
The results of the simulation, however, show an output noise density lower than what would be expected from kt/C. (The density, is, however, larger than 4kTR... and I have verified that the verilog SH block samples the capacitor during the hold phase). The simulated noise density is also a strong function of the series switch resistance.
I have also noticed that when I run a sim using a MOS switch, that there is a large 1/f component to the simulated noise contribution. This is also somthing I would not expect to see.
Any suggestions?
Ben ???
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