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simulating/predicting synth divider noise (Read 3023 times)
mikev
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simulating/predicting synth divider noise
Nov 18th, 2003, 10:52am
 
I'm trying to predict synthesizer divider noise, but my results seem to be optomistic.

I've run PSS and PNOISE in time domain method to only sample noise on the edge that matters.  I then apply (32) from http://www.designers-guide.com/Analysis/PLLnoise.pdf.  However, when I then do 10log(Sphi(f)), my dBc number seems too optomistic.

Example:
Output noise at 1kHz: 28.8uV/sqrt(Hz)
fo=62.5kHz
SR=35GV/s

Sphi(1kHz) = [2*pi*62.5kHz/(35GV/s)]^2 * (28.8uV/sqrt(Hz))^2
Sphi(1kHz) = 104.4e-21 rad^2/Hz
10*log(104.4e-21) = -190 dBc

My assumptions:
PSS is run at 62.5MHz, not 62.5kHz, to speed simulation.  I don't feel this is a problem, since this is a synchronous counter.

I've simulated with different max sidebands to make sure the noise folding is accounted for.

I'm only using noise at a single point, do I need to integrate the noise over the transistion of the output signal?

Am I correct in thinking that 10*log(Sphi(f)) gives me a dBc, because I'm in radians? I.E., Sphi(f) is the noise at the end of a vector, which is always related normalized?

Thanks.
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Ken Kundert
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Re: simulating/predicting synth divider noise
Reply #1 - Nov 19th, 2003, 8:44am
 
I would expect the phase noise to be small because you are running at such a low frequency. With the slew rate being 35GV/s your circuit is obviously quite fast. It can clearly switch in much less than 1ns, and yet 1ns represents only about 0.02 degrees of a 62.5kHz signal.

Remember, that with a constant amount of jitter, that phase noise drops with the signal frequency because it represents the amount of jitter relative to the length of the period, and the period is growing.

-Ken
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