I am designing SC multibit sigma-delta modulator in 0.18 CMOS and I have a problem with (most probably!) switches at the first integrator.

My design is differential 3rd order structure with one feedback path from 4-bit quantizer. The PSD of the modulator output has DC component and severe harmonic distortion (-45..-50dB), both even and odd ones.

The feedback from the quantizer is implemented as parallel 16 SC paths coming to the input of the OTA in the 1st integrator. I tried to change 3 of 4 switches in all these paths from CMOS gates to ideal switches (I had problems with conversion when changing all of them) and the performance of the modulator become close to the predicted one (SNR around 80db, no distortion). However when I change only some switches to ideal (e.g. the ones through which the input signal comes), the performance is again poor - harmonic distortion and DC offset.

Also I compared the performance of classical 2nd order structure with single bit and multibit quantizer - single bit works fine, but when I increase the number of bits, harmonic distortion appears and for 4 bits DC offset as well.

So I guess the problem is with the switches.. All real switches are CMOS transmission gates with minimal gate length. I chosed the NMOS and PMOS width so that the RC constant would be around 1/5 of the sampling half clock cycle. The ratio between PMOS and NMOS is around 5, so that the max Ron resistance is symmetrical from both NMOS and PMOS parts.

Can such a poor behavior be because of charge injection from switches? ??? Or it comes from switch non-linearity (as I've written above I tried to back it as linear as possible)? ???

I would be very grateful if anyone could propose any hints for my problem.

Alex.

Hi boa,

Is the single-bit vs multi-bit simulation performed with non-ideal switches? I have a hypothesis regarding your problem, but to be sure you must check with your design.

Transmission gates are good in transmitting close to ground voltages (through the NMOS) and close to VDD voltages (through PMOS), but they typically have a conduction gap between VDD/2 and 2/3VDD, especially at low supply. In simulation, you can try to improve this by raising the clock voltages to let's say 2.2 or 2.5V. This should give significantly better results. Does it in your simulation? In a single-bit modulator, you only have high and low voltages, in a multi-bit you have voltages around VDD/2 which may explain why you have bad results.

Of course this is not a solution for a real life design, due to reliability problems due to excessive gate voltage. You should minimize the number of switches in series in the signal and feedback paths.

Paul