Paul
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Hi boa,
Is the single-bit vs multi-bit simulation performed with non-ideal switches? I have a hypothesis regarding your problem, but to be sure you must check with your design.
Transmission gates are good in transmitting close to ground voltages (through the NMOS) and close to VDD voltages (through PMOS), but they typically have a conduction gap between VDD/2 and 2/3VDD, especially at low supply. In simulation, you can try to improve this by raising the clock voltages to let's say 2.2 or 2.5V. This should give significantly better results. Does it in your simulation? In a single-bit modulator, you only have high and low voltages, in a multi-bit you have voltages around VDD/2 which may explain why you have bad results.
Of course this is not a solution for a real life design, due to reliability problems due to excessive gate voltage. You should minimize the number of switches in series in the signal and feedback paths.
Paul
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