I've been designing a multi-bit sigma-delta modulator and now I am testing its performance with Element Selection Logic (modified Data Weighted Averaging (DWA) in my case). The circuits in the DWA are digital - log shifter, counter, regs etc. Right now I have added just the 16-bit log shifter to the schematics (the only part of DWA that is in the feedback signal path). However the simulation time in Spectre has increase dramatically - from 8 to 15 hours for 2.5k points.

I've heard from Mentor Graphics that it is possible to separate digital and analog parts in ELDO and use different precision for them, thus speeding up the simulations. Is it possible to do something like that with Cadence tools?? Or maybe it would be reasonable to use AHDL models for digital parts??

A more general question - are there any ways for fast simulations of sigma-delta loops?? I have read Ken's paper about noise estimation of modulator using SpectreRF PSS techniques, but as far as I understood, this methodology can only estimate the noise floor in the output PSD due to devices noise and not harmonic distortion. Am I right??

For me it is important to see THD and SFDR because of input switches non-linearity.