There aren't really any. Most mixed-signal designs are done using standard digital cell libraries. Certainly all the mixed signal designs I've done have used normal digital cell libraries. Occasionally you need a digital cell (in the analog parts of the design) which isn't quite right in the digital library (wrong drive strength, thresholds etc) which you might need for a specific purpose, but in general I can't think of any special requirements.

Of course, it's useful to have those digital cell libraries using inherited connections, so if you need to use the digital cells on an analog supply, it's easy to do so, but apart from that I'd say there are no special requirements.

Regards,

Andrew.

Often digital cell libraries, if they have schematics, have the power supplies as global connections rather than pins. This is because digital designers don't normally want to have to connect up the power supplies in their verilog code - which may have come out of synthesis anyway.

The trouble with global supplies is that often you don't want digital components which are in an analog portion of the design to be on the same supply as the rest of the digital - you may want them to be on an analog supply. But global means global, and so global supplies prevent you from being able to use multiple supplies.

Cadence DFII has this mechanism called "inherited connections" which allows a connection inside a cellView to inherit it's connection via a property set one or more levels above in the hierarchy.

For example, I can define a net in a schematic, with a net expression on it saying that the net is governed by a property called "pvdd", with a default value vdd!
This means that if I don't do anything, and use it as normal, it will end up connected to the global net vdd!.
However, I could set a property value for pvdd on an instance, several levels up the hierarchy, indicating that pvdd to should bind to a net (at that level) called "avdd".

What happens for many netlisters is that the netlister will then insert extra connections through the hierarchy to wire this up, although the schematic doesn't need to be physically wired up. Other simulators (like AMS Designer) can resolve these inherited connections at elaboration time (effectively when the hierarchy is flattened).

I could then have one block using the cell which has pvdd set to avdd, another set to bvdd, and another where it is not set and defaults to vdd!. Consequently I have three blocks, using the same cell, which doesn't have pins for the power supply, yet they are connected to different things.

That's the idea - it's very useful indeed. You can think of it as a means of making connections via properties, rather than via physical wires in the schematic.

Regards,

Andrew.

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That's one of the main goals of inherited connections - you can have a set of digital standard cells that you don't need to copy and modify to use in the analog domain (unless of course you need to change the design). You can still follow the connections using inherited connections.

Andrew.