ywguo
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Hello,
I have never used the inherited connections. But I always modify the symbol of the standard cell, puting pin vdd and vss on it. Then I can connect them arbitrarily to vdd, vss, avdd, avss, etc. It is more visual in the schematic. :)
As to some possible special requirement, what I can thought is that the P/N ratio is too small sometimes. Then the rising edge and falling edge is not symetrical, rising edge slower, and falling edge faster.
For high speed mixed signal circuit, that is a problem. For e.g., serdes, PCI-express, SONET, those circuits operates above GHz. The designer must be very careful to keep the rising edge and falling edge balance. Otherwise the clock signal above GHz will become distorted, even disapear.
For that design, it is a bad news that the standard cell often have a low P/N ratio in order to get high density. Most standard cells have P/N ratio of about 1.5 to 2, while the Beta of PMOS is more than 3 times of the Beta of NMOS in very deep submicron process, even 4 ~ 5 times.
So sometimes the designers have to design the cells by themselve.
And now I am designing pipelined ADC. In this design I use some standard cell. I found the nonoverlapping clock has slower rising edge, about two times of falling edge. I suspect that affect the open and close of the complement MOS switch. So I am checking it and maybe rebuild all the digital cells.
Best regards,
Yawei Guo
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