ywguo
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Hello,
When I simulate the settling behaviour of MDAC used in a stage for pipelined ADC, it shows very large overshoot (about 100mV) at SS corner, 3.0V, 125C.
The MDAC lies in a conventionally 1.5bit stage, made of a telescopic opamp and several capacitors and switches.
But at TT corner, 25C, 3.3V, and FF corner, -40C, 3.6V, the overshoot is very small (less than 10mV) and the telescopic opamp settles very fast.
The AC analysis shows that the phase margin is more than 75 degree. Especially when the capacitance loading is large, the phase margin approaches 80 degree. I though that is normal for a two-pole system when its settling behaviour is the most concern.
Could you help me? Tell me how to improve the settlng behaviour.
Best regards,
Yawei Guo
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