The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
May 5th, 2024, 8:29am
Pages: 1
Send Topic Print
Simulation using Cadence virtuoso layout (Read 1561 times)
Vignesh
Guest




Simulation using Cadence virtuoso layout
Jul 09th, 2004, 3:13pm
 
Hi,

Anyone  knows how to simulate the layout after finishing DRC, extraction and LVS. I use analog environment and also give stimuli like Vdd=2.5V and gnd=0V. But when I simulate the layout I still get 0V output. btw I am doing a transient simulation. Can anyone help me with this ?

Thanks
-vignesh
Back to top
 
 
  IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.