I am using the veriloga "generate" statement  in the veriloga definition for a 28 bit adder used inside a delta sigma modulator.  

It takes an unusually long time for the syntax check to be completed.   There are no errors and the adder produces the correct results in simulation.  However the simulation takes a long time to get started.

Origially I had implemented the adder with a cascase of two bit full adders.  I thought I could speed up the simulation by consolidating the adders into one defintion file.  However the consolidated 28 bit definition is even slower than the cascade of two bit adders.

I suspect that this is due to some inefficiency in the "generate" statement.  Is that the case?
Is there a better alternative?

Any comments would be greatly appreciated.

--Nader

Thank you for your reply Andrew.

Here is the entire code below.  The formatting got a bit messed up when I cut and pasted it here but I hope that it is readable.

Basically the code tries to add two values x and y which are 28 bits long and output the sum and the carry.

Regards,

Nader


`include "constants.h"
`include "discipline.h"

module pll_add28_va(z, x, y);
output [28:0] z;
electrical [28:0] z;
input [27:0] x;
electrical [27:0] x;
input [27:0] y;
electrical [27:0] y;

parameter real vlogic_high = 1.2;
parameter real vlogic_low = 0;
parameter real vtrans = (vlogic_high + vlogic_low)/2;
parameter real tdel = 60p from [0:inf);
parameter real trise = 40p from (0:inf);
parameter real tfall = 40p from (0:inf);

  integer  a[27:0], b[27:0], c[27:0], p[27:0], g[27:0];
  real S_val[27:0],i;
  real CO_val;

 analog begin

    generate i (0,27,1) begin
       a[i] = V(x[i]) > vtrans;
       b[i] = V(y[i]) > vtrans;

           @ (cross(V(x[i]) - vtrans, 1))   a[i] = 1;
           @ (cross(V(x[i]) - vtrans, -1))  a[i] = 0;

           @ (cross(V(y[i]) - vtrans, 1))   b[i] = 1;
           @ (cross(V(y[i]) - vtrans, -1))  b[i] = 0;


//generate Pi and Gi
     p[i] = a[i] ^ b[i];
     g[i] = a[i] & b[i];
     if(i >= 1) c[i] = g[i-1] | (p[i-1] & c[i-1]);
                  else c[i] = 0;    

     S_val[i] = (c[i] ^ p[i]) ? vlogic_high : vlogic_low;
     V(z[i]) <+ transition( S_val[i], tdel, trise, tfall);
 end            



    CO_val = (g[27] | (p[27] & c[27])) ?    logic_high :vlogic_low;

    V(z[28]) <+ transition( CO_val, tdel, trise, tfall);

  end

endmodule