I think this should work... I've not done it for a while, but I think it should be OK:
In the analog control file, you can add lines:
Code:saveNodes options rawfmt=sst2 rawfile="trans1.tran"
save top.block1.block2.sigName1 top.block1.block2.sigName2
You can then save (into another file) hierarchical paths into subckt blocks.
However, why are you including spectre netlists? If those spectre netlists came from Composer schematics, would it not be better to get them in Verilog-AMS format (the AMS Designer interface will do this for you)? That way you can see everything in simVision.
Regards,
Andrew.