In VDD=3.0~3.6V, 10bit, 60MHz ADC design, someone told me that boostrapped SW must be used in T/H circuit to guarantee sufficent SNDR. However, I believe HSPICE or Spectre is accurate in distortion simulation, so if the result is good enough, boostrapped SW can be replaced by normal CMOS SW for simplicity. Am I right?

Basically, I think that is very difficult.

1. T/H stage can achieve high linearity with gain-boost technique. The sampleing is input dependent if just using a very large complement switch.

2. We can choose NMOS transistors as input switch if using gain-boots technique without concern of input swing. But we must use complement switch without gain-boost technique. PMOS transistors has lower mobility, that deteriorate the input bandwith.

3. To lower the on-resistance of input switch, you must ether increase the aspect ratio or Vgs. Gain-boost is a good choice to avoid very large aspect ratio. Very large aspect ratio increase parasitic capacitance and feedthrough in hold phase.

I hope that is clear.

Best regards,
Yawei

10-bit linearity should be achieved without much problems if you use bottom plate sampling techniques, which forces the bottom plate of capacitor opened before the top plates does, and thus avoid signal-dependent charge injection errors. Also, in supply-voltage of 3 V, your switches should have quite large overdrive with reasonable input swing, and your switches size can be choosed quite small.

Yes, boostrapped SW can have a some effect to reduce the parasitic cap used in SW, but you must still use bottom plate sampling techniques since your sources of SW still follow the input signals and thus causing distortion. Also, boostrapped SW consumed larger power.