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codec

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nonoverlap delay in Pipelined ADC
Oct 13^th, 2004, 8:04pm

I am now designing a 10bit 60MHz pipelined ADC, and it is my first time.
I am quite puzzled in selecting the delta T for nonoverlap delay. Past experience in delta-sigma ADC tells me that such valued should not be too short because of distortion. (In fs=6.144MHz 16bit ADC, I set it to 3.2ns). So I plan to set it to about 1.5ns. However, this value forces OTA to settle within 5~6ns. SNDR degradated in worst case. Instead, 1ns delta T led to fairly good result.
As I lack experience in pipelined ADC, would someone help me?

Thanks.

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terryssw New Member Offline Posts: 5	Re: nonoverlap delay in Pipelined ADC Reply #1 - Oct 16^th, 2004, 9:50am I don't quite familir with Sigma-Delta ADC that why small non-overlapping delay leads to large distortion, but in pipelined ADC the non-overlapped delay can be minimize such that the clock still non-overlap with safety margins in worst cases. Leaving 500 ps is enough for most applications.
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codec

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Re: nonoverlap delay in Pipelined ADC
Reply #2 - Oct 18^th, 2004, 9:35am

Thanks, Terryssw.
I am hesitate to reduce the nonoverlap delay since the wire resistance, capacitance and loading might worsen the nonoverlap effect. I use a large buffer to drive the clocks and in each stage, a sub driver. What do you think of it?
Anyway, I will follow your advice to set the worst case delay to about 0.5ns. Do you run post-layout simulation to confirm the performance while designing a pipelined ADC? I wil try to do so this time.

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terryssw

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Re: nonoverlap delay in Pipelined ADC
Reply #3 - Oct 21^st, 2004, 1:02am

Of course, post-sim is good if you can afford the time needed. The 0.5ns non-overlp time is for the most worst case, i.e. including all parasitic wire resistance, cap, etc. Also, 0.5ns non-overlap time is usully for higher speed ADC(while your case is in medium speed). In lower-speed, this time can larger and just to make sure the opamp had enough settling time is enough.

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