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codec Junior Member Offline Posts: 14	THA Design Nov 03^rd, 2004, 4:29am Hello, I met difficulty in THA design of the pipelined ADC. The T/H circuit has a worst case THD of 72dB@1.875MHz(fs=60MHz) but 55dB@58.125MHz(fs=60MHz). In such case, what should I focus on in order to improve the performance? Any adivce or recommended paper? Thanks a lot!
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ywguo

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Posts: 943
Shanghai, PRC

Re: THA Design
Reply #1 - Nov 5^th, 2004, 6:23am

Hi,

First of all, I want to know how do you measure THD of the THA. :)

When I simulate THA, I measure THD using FFT analysis. It is important to control the start time and step of FFT because the Track and hold is a one-order sample and hold. Do you think so?

About your problem, THD decreases as the input frequency increases because of finite input bandwidth. I think you should lower the on-resistance of input switch or lower the capacitance of the sampling capacitor.

Best regards,
Yawei

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codec

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Posts: 14

Re: THA Design
Reply #2 - Nov 5^th, 2004, 7:51am

Thanks, ywguo!
I also use FFT to measure THD. I set fin=fs/32 and take 64 points or above to calculate FFT.
The Fu of THA amp is about 600MHz and it is a flip-around THA structure. I also suspected that Ron of SW was too high, but when I used ideal SW with Ron as low as 50~100ohm, the THD was not improved. (It is also this simulation let me select CMOS SW instead of boostrapped SW)
What about your simulation result?

BTW, I use Spectre .

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microant2000

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Re: THA Design
Reply #3 - Nov 7^th, 2004, 10:49pm

hello,
I want to know the resolution of your THA,and what do you mean in your article "55dB@58.125MHz",it seems that the measure is in the undersampling condition.
Do you measure the sample switch' THD? it will limit the THA performance.about the on-resistance , i think you should make it constant ,not lower.
sorry, my English is poor, i hope you can understand my ideal. Cheesy

Best regards,
microant

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codec Junior Member Offline Posts: 14	Re: THA Design Reply #4 - Nov 9^th, 2004, 3:25am Thanks, MicroAnt It is true that constant Ron(Vin) is of most importance. These days, I chaned the switch to bootstrapped type and archieved a better THD of 65dB@61.875MHz. (undersampling mode) But I am wondering whether such simulation is necessary.
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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: THA Design Reply #5 - Nov 15^th, 2004, 3:53am Hi, Codec, Have you measured the on-resistance of the switches? I wonder the relationship between the resistance and the THD. The THD of the THA is necessary because it decides the THD of whole ADC. Yawei
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codec Junior Member Offline Posts: 14	Re: THA Design Reply #6 - Nov 16^th, 2004, 7:23pm Hello, Yawei Ron is around 60~100ohm in my design. I mean whether it is necessary for me to simulate the circuit under the condition of "undersampling"? In real application, would such case occur?
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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: THA Design Reply #7 - Nov 19^th, 2004, 7:16pm Codec, Ron is around 60~100Ohm for bootstrapped swtich? That is very near Ron in my design, which is a 40MHz, 10bit IF-samping ADC. The undersampling depends on your application. For eg., an IF-sampling ADC used in DVB-C demodulator. What is your application? Best regards, Yawei
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codec

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Posts: 14

Re: THA Design
Reply #8 - Nov 30^th, 2004, 2:52pm

Hi, Yawei
Sorry for my late reply. I was busy working these days.
My current design is for the request of a custom. It is said to be a video application.

BTW, have you done the post-layout simulation?
When I was doing the post simulation on the THA block, I found that the THD degradated for near 10dB. I am trying to find the problem. Have you any ideas?

Thanks.

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