PAC is considering the whole signal (over a complete clock cycle) when computing the gain. If your signal spends half its time at zero due to a reset phase, that will effectivly reduce your gain by half (6 dB).

To avoid this problem, use the idealized sample-and-hold given in http://www.designers-guide.com/Analysis/hidden-state.pdf and sample the output of you circuit at the time the subsequent stage would normally sample it. Then have PAC compute the transfer function to the output of the sample and hold. This gives a much better measure of the effective gain of you stage, though it does add some sin(x)/x distortion.

-August