I am interested if anyone knows a topology that can generate frequencies that are a non integer division of the input.  In paticular I am interested in something that does half steps such as divide by 5.5.  I can use the falling ege of the input, but any variation in duty cycle will cause jitter on every other edge.  Are there any methods that will not create this edge jitter.

Thanks

Try this!! this is a rate multipiler.. the values of M and N are decided by the GCD.. for 5.5 these will be 11 and 2.

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_signed.all ;

entity rate_multiplier_demux is
port(
    arst                :in  std_logic ;
    clk_vco             :in  std_logic ;
    clk_out             :out std_logic
   ) ;
end rate_multiplier_demux ;


architecture rate_multiplier_demux of rate_multiplier_demux is



component delayst_demux is
generic(D               :integer range 1 to 50 := 1 ;
       in_width        :integer range 1 to 50 := 2) ;

port(
   arst               :in  std_logic ;
   clk                :in  std_logic ;
   clk_en             :in  std_logic ;  
   data_in            :in  std_logic_vector(in_width - 1  downto 0) ;
   data_out           :out std_logic_vector(in_width - 1  downto 0)
   );
end component ;

component demux_vector_sel is
generic(in_width    :integer range 1 to 20 := 2) ;
port(
    data_sel          :in  std_logic ;
    data_in1          :in  std_logic_vector(in_width - 1 downto 0) ;
    data_in2          :in  std_logic_vector(in_width - 1 downto 0) ;
    data_out          :out std_logic_vector(in_width - 1 downto 0)
   );
end component ;



signal GND             :std_logic ;
signal VCC             :std_logic ;

signal inv_clk_vco     :std_logic ;

signal M                     :std_logic_vector(11 downto 0) ;
signal N                     :std_logic_vector(11 downto 0) ;
signal A_reg           :std_logic_vector(11 downto 0) ;
signal A_reg_in        :std_logic_vector(11 downto 0) ;
signal A_reg_l         :std_logic_vector(11 downto 0) ;

signal B_reg           :std_logic_vector(11 downto 0) ;
signal B_reg_l         :std_logic_vector(11 downto 0) ;



begin

GND  <=  '0' ;
VCC  <=  '1' ;
M       <= "000001000011";
N       <= "010000000000";
inv_clk_vco  <= not(clk_vco) ;

A_reg    <= A_reg_in - M  ;

label3 :component delayst_demux   generic map(1 , 12) port map(arst , clk_vco , VCC , A_reg , A_reg_l) ;

B_reg    <= A_reg_l + N  ;

label4 :component delayst_demux generic map(1 , 12) port map(arst , inv_clk_vco , VCC , B_reg , B_reg_l) ;

label5 :component demux_vector_sel generic map(12) port map(A_reg_l(11) , A_reg_l , B_reg_l , A_reg_in) ;


clk_out <= A_reg_l(11) ;


end rate_multiplier_demux ;

-- delay st!!
library ieee ;
use ieee.std_logic_1164.all ;
entity delayst_demux is
generic(D         :integer range 1 to 50 := 1 ;
       in_width  :integer range 1 to 50 := 2) ;

port(
    arst         :in  std_logic ;
    clk          :in  std_logic ;
    clk_en       :in  std_logic ;  
    data_in      :in  std_logic_vector(in_width - 1  downto 0) ;
    data_out     :out std_logic_vector(in_width - 1  downto 0)
   );
end delayst_demux ;

architecture delay of delayst_demux is

component reg
generic( M :integer := 15) ;
port(
    arst         :in  std_logic ;
    clk          :in  std_logic ;
    clk_en       :in  std_logic ;
    data_in      :in  std_logic_vector(M - 1 downto 0);
    data_out     :out std_logic_vector(M - 1 downto 0)
   );
end component ;

type state is array(D  downto 1) of std_logic_vector(in_width - 1  downto 0) ;
signal temp : state ;
begin

label1 :for i in 1 to D  generate
label2 :if(i = 1)  generate
label3 :reg generic map(in_width) port map(arst , clk , clk_en , data_in , temp(i)) ;
       end generate ;
label4 :if(i /= 1)  generate
label5 :reg generic map(in_width) port map(arst , clk , clk_en , temp(i - 1) , temp(i)) ;
       end generate ;
       end generate ;

data_out <= temp(D) ;

end delay ;

--demux_vector sel
library ieee ;
use ieee.std_logic_1164.all ;

entity demux_vector_sel is
generic(in_width       :integer range 1 to 20 := 2) ;
port(
    data_sel          :in  std_logic ;
    data_in1          :in  std_logic_vector(in_width - 1 downto 0) ;
    data_in2          :in  std_logic_vector(in_width - 1 downto 0) ;
    data_out          :out std_logic_vector(in_width - 1 downto 0)
   );
end demux_vector_sel ;

architecture demux_vector_sel of demux_vector_sel is

begin

process(data_sel ,  data_in1 , data_in2)
begin
case data_sel is
when '0'     => data_out <= data_in1        ;
when '1'     => data_out <= data_in2        ;
when others  => data_out <= (others => 'Z') ;
end case ;
end process ;

end demux_vector_sel ;      

--reg used in delay st

library ieee ;
use ieee.std_logic_1164.all ;

entity reg is
generic( M :integer := 16) ;
port( arst          :in   std_logic ;
     clk           :in   std_logic ;
     clk_en        :in   std_logic ;
     data_in       :in   std_logic_vector(M - 1 downto 0) ;
     data_out      :out  std_logic_vector(M - 1 downto 0)
   );
end reg ;

architecture reg of reg is

signal temp_data_out :std_logic_vector((M - 1) downto 0) ;

begin
process(arst , clk , clk_en , data_in , temp_data_out)
begin
if(arst = '1')  then  
temp_data_out <= (others => '0') ;
elsif(clk'event and clk = '1') then
if(clk_en = '1') then
temp_data_out <= data_in ;
else
temp_data_out <= temp_data_out ;
end if ;
end if ;
end process ;

data_out <= temp_data_out ;

end reg ;