Paul
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[quote author=Vivek Chandrasekhar link=1107456403/0#2 date=1107559339]Hi Paul,
Thanks for your suggestions. I am working on ldv 5.1 simvison tool in Verilog AMS with Vdd=1.2V for IBM 0.13 micron technology. I would like to know how to make my model detail enough so that it can compute current in all branches. As you said, I can compute the current manually for all my subcircuits in my design and multiply it by Vdd to give me average power disappiation . I remember in Cadence spectre where in the spectre computes the average power disappiaton all by itself in the result brower. Could you suggest me any technique so that the simvison model calculates the average power.
Thanks
Vivek [/quote]
It is not very clear whether you want to obtain the total power from your simulation or want to specify in the model what the expected consumption is. In the first case, you have to model each current and voltage source as such, each current mirror as a copy of the initial current. If all your branches are defined with the correct directions, the sum of all currents will be delivered by the power source (VDD), from which you can then derive the total power. Of course this means that you have already a very good idea of the final transistor level design, in order to know the current in each branch.
If your model is intended for pre-design system analysis, you probably don't know these values yet, except maybe from an estimation based on previous designs. If your model is for validation after the transistor level design, then of course you can define very accurately the values in the model. But in the latter case, using the statement mentioned by Andrew would probably be much simpler than writing such a detailed model.
Paul
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