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Vivek Chandrasekhar Guest	Verilog AMS Design simulation Feb 03^rd, 2005, 10:46am Hi, I have designed a 4 bit current steering Digital to analog conveter using Verilog AMS. I am interested in knowing the average power disappiaton of my design. How should I go about it? Thanks Vivek
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Paul

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Re: Verilog AMS Design simulation
Reply #1 - Feb 4^th, 2005, 1:06am

Hi Vivek,

if your model is detailed enough to contain the currents flowing in all branches, you should be able to consider the current flowing on you power source (VDD). But notice that the accuracy fully depends on the accuracy of your model. Each current you ommit in the description will be missing in the resulting power measurement.

Paul

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Vivek Chandrasekhar

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Re: Verilog �AMS Design simulation
Reply #2 - Feb 4^th, 2005, 3:22pm

Hi Paul,

Thanks for your suggestions. I am working on ldv 5.1 simvison tool in Verilog AMS with Vdd=1.2V for IBM 0.13 micron technology.
I would like to know how to make my model detail enough so that it can compute current in all branches. As you said, I can compute the current manually for all my subcircuits in my design and multiply it by Vdd to give me average power disappiation . I remember in Cadence spectre where in the spectre computes the average power disappiaton all by itself in the result brower. Could you suggest me any technique so that the simvison model calculates the average power.

Thanks

Vivek

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Andrew Beckett

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Re: Verilog AMS Design simulation
Reply #3 - Feb 7^th, 2005, 12:53pm

If you're talking about the pwr output that spectre does,
then that is something that each device and model is intended to output. There's a task in Verilog-A ($pwr() I think) which allows you to tell the simulator how much power your circuit is consuming - and then spectre sums it up appropriately.

The alternative is to make sure that there are branches in your model which reflect the power consumption, between the right nodes, and then measure the power by looking at the current flow into the circuit (as has been stated in previous posts).

Andrew.

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Vivek Chandrasekhar Guest	Re: Verilog �AMS Design simulation Reply #4 - Feb 7^th, 2005, 4:33pm Hi Andrew, Thanks for your mail. Is there any task in Verilog AMS which tells us how much power the circuit is consuming just the same way as in Verilog-A. Thanks Vivek
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Andrew Beckett

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Re: Verilog AMS Design simulation
Reply #5 - Feb 7^th, 2005, 10:27pm

Vivek,

The $pwr task (sorry, I don't remember exactly what it is called, and don't have a language reference handy) should work in AMS Designer too (in Verilog-AMS).

However, the point is that you call this in your model to tell the simulator how much power your model is consuming - it's not something that causes the simulator to work out how much power your model is consuming.

Read the documentation on this... I did manage to do a
quick search of the docs - in IC5141 it's in Chapter 9 of both the Verilog-A manual and the Verilog-AMS manual.
(it is called $pwr - my memory was correct).

Regards,

Andrew.

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Paul

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Re: Verilog AMS Design simulation
Reply #6 - Feb 8^th, 2005, 3:16am

[quote author=Vivek Chandrasekhar link=1107456403/0#2 date=1107559339]Hi Paul,

Thanks for your suggestions. I am working on ldv 5.1 simvison tool in Verilog AMS with Vdd=1.2V for IBM 0.13 micron technology.
I would like to know how to make my model detail enough so that it can compute current in all branches. As you said, I can compute the current manually for all my subcircuits in my design and multiply it by Vdd to give me average power disappiation . I remember in Cadence spectre where in the spectre computes the average power disappiaton all by itself in the result brower. Could you suggest me any technique so that the simvison model calculates the average power.

Thanks

Vivek [/quote]

It is not very clear whether you want to obtain the total power from your simulation or want to specify in the model what the expected consumption is. In the first case, you have to model each current and voltage source as such, each current mirror as a copy of the initial current. If all your branches are defined with the correct directions, the sum of all currents will be delivered by the power source (VDD), from which you can then derive the total power. Of course this means that you have already a very good idea of the final transistor level design, in order to know the current in each branch.

If your model is intended for pre-design system analysis, you probably don't know these values yet, except maybe from an estimation based on previous designs. If your model is for validation after the transistor level design, then of course you can define very accurately the values in the model. But in the latter case, using the statement mentioned by Andrew would probably be much simpler than writing such a detailed model.

Paul

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