hi. I have a quesion to ask, and highly appreciate if anyone drop your comments.
i am working on a capacitive sensor, and i need to model it as a time-varying capacitor. i am thinking of model it as a voltage controlled capacitor. this behavior level model will be combined with circuit simulator- cadence to simulate the systematic behavior of my interface circuit. can someone tell me how to create such a model in cadence?
???

not sure, need to check it out. what should i do if i have access to verilogA?

thank you, ken.

but as a circuit designing guy, i never create such a fully-customed component before. i just don't know how to access verilogA with cadence, can you recommend some quick online manual or briefly tell me how to do that?

thanks.

HE Lin

thank you. Ken and Andrew, I have already finished the modeling of time-varying capacitor.
here i have something to share with other guys who may have similar problems.

Please follow the below steps to create a symbol out of the verilog-a code. Then you can instantiate this symbol in you design and make use of the same.



1)       In CIW, File->New->Cell View

2)       Give a Library name, Cell name and choose Tool as “VerilogA-Editor” from cyclic field and press OK.

3)       This will open a VI editor. This will contain some default lines, delete these lines and paste your verilog-a code in this file.

4)       Save the file by typing :wq in vi editor

5)       This will create a veriloga view for this code.

6)       After few seconds, it will ask if you want to create a symbol view for the same. Press Yes. This will create a symbol view for your code.

7)       You may instantiate this symbol in your schematic and make use of the same.



Hope this helps.