I am able to plot fT vs. ID for a MOS transistor in Cadence. I use an AC analysis with the SpectreS simulator from the Analog Design Environment.

In the past, when designing high-speed amplifiers, I used the fT vs. ID curve to find the optimum transistor size and bias. Since the amplifiers were operating in the small-signal region, I didn’t have to question whether the conclusions derived from the fT vs. ID curve were valid or not.

I am currently trying to design a 2.5 Gbps output buffer in CMOS 0.18 um. I use CML, so the transistors are dealing with a 400 mV signal (800 mV p-p differential). Since the transistors are not operating in the small-signal region, I am questioning whether the conclusions derived from the fT vs. ID curve are valid or not. In the past, I have sized and bias my transistors using a trial and error approach. By monitoring the output eye diagram, I try to 1) minimize inter-symbol interference (ISI), 2) reduce rise and fall times, 3) minimize ringing, and 4) get the right amplitude. I am now looking for a more methodological/logical approach.

In summary, my question is: Is the fT vs. ID curve any useful when designing for large-signal? If yes, why? If not, what tricks do the high-speed (1 to 10 Gbps) experts use for transistor sizing and biasing when designing for large-signal operation?