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Verilog-AMS training (Read 3324 times)
learnams
New Member
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Posts: 1
Verilog-AMS training
Feb 23
rd
, 2005, 5:35pm
Hi,
Are there any short training sessions for analog behavioral modeling in Verilog-AMS or VHDL-AMS? I am looking for some thing where instead of learning just by reading a book, we can have somebody explaining the concepts to us and try out some labs.
Thanks!
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Andrew Beckett
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Life, don't talk to
me about Life...
Posts: 1742
Bracknell, UK
Re: Verilog-AMS training
Reply #1 -
Feb 23
rd
, 2005, 9:31pm
Cadence offer a "Virtuoso AMS Designer" class. See the course catalog at
http://learning.cadence.com/ns-bin/docentnsapi/lms,learning.cadence.com,2151/?CM...
Expand the Custom IC Design part of the catalog, and you'll find it there.
This class explains not only how to use the tool, but the concepts in the Verilog-AMS language. There is a section on VHDL-AMS too.
More details at
http://learning.cadence.com/ns-bin/docentnsapi/lms,learning.cadence.com,2151/SID...
Note, I'm not sure the duration is correct there. It was a 3 day class when I taught it recently. It's quite a good class, in my opinion.
Regards,
Andrew.
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