Sid
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Hi,
My understanding is that the front-end sample-and-hold alone determines if an ADC can undersample with high-performance (assuming the clock jitter is somehow made low-enough).
Assuming a traditional gain-of-1 flip-around kind of S/H, I beleive, the ability to sample a very high-frequency input signal depends ONLY on the sampling switch linearity and input sampling bandwidth. By input sampling bandwidth, I mean w3dB = 1/RC, R = sampling switch resistance and C = sampling capacitor. Is this understanding correct?
Suppose I have a very high-linearity bootstrapped switch to sample the high-frequncy input signal, my 10 MS/s 12-bit ADC should be able to sample and quantize a 100 MHz signal (provided my bootstrapped switch and sampling capacitor can handle a 100 MHz signal with high-linearity and have a large enough BW). Is this correct?
In other words, do I need to worry about the performance of the OTA in the input S/H amplifier for undersampling performance or is it ONLY the boostrapped sampling switch that determines undersampling performance?
Any inputs will be appreciated.
Thanks, Sid
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