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pnoise analysis for switched-C circuits (Read 2819 times)
rjiang
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pnoise analysis for switched-C circuits
Jun 13th, 2005, 11:27am
 
Hi, I want to estimate total noise (thermal,1/f) of a switched-C circuit.  The circuit is pretty big and has correlated-double sampling to reduce 1/f noise.

I started pnoise analysis on a very simple circuit. It has only one NMOS switch and a 1pF cap.  clock is 10MHz. I ran pnoise analysis and integrated the total noise. The result is much higher than KT/C (c=1pF).

I have following questions:
[1] Is pnoise the right way to estimate switched-C circuit noise?
[2] the noise floor is much higher than 4KTR.  In pnoise analysis, "noise type" is time domain.  If noise type is source, noise floor looks OK.  But I do not  know the exact time for this analysis.
[3] output noise should be periodic every 10MHz.  But it is like a continuous-time spectrum without repeating or aliasing.
[4] If correlated double sampling is used, can pnoise take this into account?

thanks,

R.J.
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Ken Kundert
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Re: pnoise analysis for switched-C circuits
Reply #1 - Jun 13th, 2005, 12:37pm
 
Take a look at http://www.designers-guide.org/Analysis/sc-filters.pdf.

And yes, PNoise can account for correlated double sampline.

-Ken
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