Hi,
I followed the example concerning jitter measurement that is on page 45 of Ken's paper "Predicting the phase noise and jitter of PLL-based frequency synthesizers" .   When I simulate the VCO/10000 circuit on its own, I get an Sphi of -60db/Hz @ 1KHz offset. There is approximately a 50db difference between what I get and what I see in figure 18 of the paper.
I 've repeteadly checked the code and I wonder if trere is something I haven't considered. Thanx a lot.

Hi,
I have some additional questions concerning the MATLAB code. The PSD figure (page 46) in Ken's paper has a frequency range from 300Hz to 100KHz.
I simulate a PLL that has a VCO output frequency of 1G and a frequency divide ratio of 4. Because the
ratio is small I simulate it for 10us and I set the outstart variable that exist in VCO's code at a value of 1us.
In matlab, the frequency range of Sphi that I get, varies from 500Khz to 100MHz which is quite different fron the paper.
My questions are:
-Does the frequency at the output of the divider(250MHz in my case) affect the frequency range of the psd?
-Does the simulation time have an impact in frequncy range?
-And finally how can I take the values of Sphi for a lower frequency?

Thank a lot for the help.