Surely this will depend entirely on how the VCO is designed? I don't think a generic answer is possible. I would expect in most cases that provided the entire swing of the VCO input is within the input range of the VCO, the output frequency would usually (for most VCOs) have the lowest frequency at the minimum value of the sine wave, and the highest frequency at the maximum.

This is a bit of an odd question... perhaps there's something behind what you're asking? It doesn't make much sense to me (or rather the answer seems too obvious unless there's some detail you've omitted).

Andrew.

Hi,

there's a slight mistake in my previous post:

the tones appear @wo -2*pi*f1 and @wo+2*pi*f1
(rad/s versus Hz... )

Kind Regards,

Peter

Are you suggesting that the VCO frequency will be DC with a 0 input voltage? I'd say such a VCO would be rather hard to design! (especially if you want high frequencies out of it
as well) - except of course if the VCO simply stops working with 0 volt input...

VCOs normally have some sort of centre frequency and gain, and a finite tuning range.

Perhaps I've misunderstood your question (still)?

Regards,

Andrew.

Most "ideal" VCO models would still be based around a
centre frequency. Even ideal models need to be vaguely model reality!

Andrew.

Yawei,

Thanks for your feedback.
I know that the implementation of the VCO dictates the power consumption. But considering only a ring oscillator made up of N single-ended inverter cells, then would it not be right to assume that P=Vd²C_LF_{vco_ave}  is approx. valid?

You said that " The power consumption of VCOs depends on its design but not acquistion or steady state."
But the time required for the PLL to lock to a new  frequency can be expressed as t_aqu = t_capture + t_lock .
For the estimation of the power consumption during the capture process, I assumed that the VCO frequency follows the variation on the control voltage. Thus, P=Vd²C_LF_{vco_ave} where F_{vco_ave} is the difference between the start frequency, and the end frequency.
The locked condition can be considered a stable state. There are no drastic changes and most of the variables like K_vco and f_vco are constant. To estimate the power during the locked range I consider that for  a non-differential implementation, at any given time, just one cell is switching. Thus the current would be something like I=V_ddC_L/t_d where t_d=1/2/N/f_vco.

Out of curiosity, how would you model the power consumption of a ring-osc. during aquisition range?

Cheers,

Thanks. This is exciting.

I was also wondering how one would express the dynamic range of a ring-oscillator? For example, in SC circuits where the main noise is kT/C we have something like DR=V_in²C_sample/(8kT).
Is there a similar equivalent for VCO's? If so, are there any references I could look up.

Thanks

Demir's work is difficult to penetrate, Hajimiri's work is seriously flawed, and MacNeill's work is largely on jitter. You might be better served taking a look at the material on this site. For example, the cyclostationary noise paper found at http://www.designers-guide.org/Theory/. You can also try http://www.designers-guide.org/Analysis/PLLnoise+jitter.pdf or http://www.designers-guide.org/Analysis/rf-sim.pdf.

For more design insights, try http://www.designers-guide.org/Books/dg-osc/index.html.