I think the main advantage of using multiple thresholds is that they can achieve low power and high performance while maintaining low leakage current.
As far as I know you could use high threshold transistors to suppress the subthreshold leakage current, while the low threshold transistors could be used to achieve the high performance. But I am not very knowledgeable on that topic.

I am not sure how to do that. I would have to study papers first in order to get familiar with that topic, such as
"Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs" by Vivek K. De
http://ieeexplore.ieee.org/iel5/6598/17617/00812579.pdf?tp=&arnumber=812579&isnu...

Maybe someone else from the forum knows.

Without going into too much detail, lower the supply voltage can reduce the power consumption. And to make a digital gate can recognize the "1" and "0", we need lower Vt MOS device. But the I/O require higher signal level to overcome the environment noise (and parasitics), so we need multi-Vt process as a low power MOS process. That we can keep the core circuit runing with low vt device with low supply voltage, and I/O with high vt devices.

In some advance process (90nm and  beyond) the off leakage current become important. Some circuit will use a medium/high vt device to turn off the supply voltage of part of circuits when we don't using it. And some circuit can story some data from low vt RAM to some high vt RAM and shootdown the low vt RAM when we are not exchange the data. And re-store the data back to low vt RAM when we need high speed operation.

Thanks everyone for the clue.