Those are not resistors. They are current controlled current sources.

-Ken

With the code you have given, if I(<p>) is zero then both I(p,n1) and I(p,n2) will be zero. Is there any reason to believe that I(<p>) should not be zero?

-Ken

The simulation result of zero is wrong.

In fact, I want to pass a dc current from spice into the verilog-a module and that the sum of the currents exiting from n1 and n2 should be equal to the current entering at p.

However, running a simulation gives a result near zero.

The spice code follows below.

vdda avdd 0 vdd
iref avdd top iref

ys1 test_switch port: top out1 out2 0

rl1 out1 0 rload
rl2 out2 0 rload

Thus, current from the iref source should enter at top which is the same node as p in the verilog-a module.

The current should exit at out1 and out2 (corresponding to n1 and n2 in the verilog-a module).

Thus, Itop = Iout1 + Iout2

This is "test_switch.va"
Code:

`include "discipline.h"

module test_switch(p,n1,n2);
  inout p,n1,n2;
  electrical p,n1,n2;
  parameter real reff1 = 1 from (0:inf);
  parameter real reff2 = 1 from (0:inf);

  analog begin
    I(n1) <+ -I(p) * reff1/(reff1+reff2);
    I(n2) <+ -I(p) * reff2/(reff1+reff2);
  end
endmodule

 

and here is my netlist:
Code:

*
simulator lang=spectre

vdda (avdd 0) vsource dc=5
iref (avdd top) isource dc=1

ahdl_include "test_switch.va"
ys1 (top out1 out2) test_switch reff1=1 reff2=2

rl1 (out1 0) resistor r=1k
rl2 (out2 0) resistor r=1k

save ys1:all rl1:all rl2:currents top out1 out2
dc1 dc dev=iref start=0 stop=5
 

I see the current divided in a 1:2 ratio.

I don't quite understand why I get a different answer if I use
       I(p,n1) <+ I(<p>) * reff1/(reff1+reff2);
       I(p,n2) <+ I(<p>) * reff2/(reff1+reff2);
I get a 1:2 ratio, and the currents aren't all zero, but the currents into test_switch ys1 don't add up to zero.

Okay, sorry. The 2 = 1 statement was a mistake, but the model as originally given is still ill-conditioned. To see it, call (p,n1) branch 1 and (p,n2) branch 2. Clearly,
I(<p>) = I(branch1) + I(branch2)
Now
I(branch1) = a1*I(<p>)
I(branch2) = a2*I(<p>)
where a1=reff1/(reff1+reff2) and a2 = reff2/(reff1+reff2). Thus,
I(<p>) = (a1+a2)*I(<p>)
which is only true if (a1+a2) is exactly equal to 1. If it is not, there is no solution. Thus, this system is singular, which would explain the odd behavior.

You would be better served reformulating the model as Geoffrey proposed. By doing so, you eliminate the ill-conditioning and cleary define the input impedance of your model to be 0 and your output conductance of both outputs to be 0.

Oh, and reff1 and reff2 are not resistors. They are numbers that determine the current division ratio between two current controlled current sources. Nowhere does the model exhibit a resistance of either reff1 or reff2.

-Ken

Yes.

-Ken