I believe the problem is more severe than that. It hard to know because we still have not yet seen the full model, but I believe that the problem is in the model itself. Even if one provided a resistor to ground from terminal p the system would still be ill-conditioned. The reason being that the model consists a current probe in series with a (pair of) current source, and the current source is forced to produce the exact same current that is measured by the probe. If this thing is driven by a resistive source, then the current is arbitrary. Any current will satisfy the circuit equations. If you force the current with a current source, then the voltage becomes arbitrary.

The model has to be rewritten so that the current through the sources is not taken from the probe.

-Ken

Now, I have removed the piecewise linear values and replaced them by linear ones. That is, reff1 is always decreasing with increasing vctr1 and vice versa.

I'm able to switch currents as wanted. However, the p node of the verilog-a module is being pulled up to VDD when I'm simulating. Although this works fine for an ideal current source, it won't work with a transistor current source.

Any suggestions? Thanks in advance.

module test_switch (p,n1,n2,s1,s2,z);                     // p/n1,n2: i/o; s1,s2: ctrl; z: avss
   parameter real ron = 10 from (0:inf);              // on resistance (ohms)
   parameter real roff = 100M from (ron:inf);          // off resistance (ohms)
   parameter real rload = 1k from (0.1:inf);           // load resistance

   inout p, n1, n2, z, s1, s2;
   electrical  p, n1, n2, z, s1, s2;

   real reff1, reff2, vctr1, vctr2;

   branch (p,n1) res1;
   branch (p,n2) res2;

   analog begin
       vctr1 = V(s1);
       vctr2 = V(s2);

       reff1 = roff+(ron-roff)*vctr1;
       reff2 = roff+(ron-roff)*vctr2;

       V(p,n1) <+ I(p,n1)*reff1;
       V(p,n2) <+ I(p,n2)*reff2;

       I(res1) <+ I(<p>)*(reff1+rload)/(reff1+reff2+2*rload);
       I(res2) <+ I(<p>)*(reff2+rload)/(reff1+reff2+2*rload);
   end
endmodule

noreng -
I still don't think you've understood the point of Ken's last post.

Even with the 10Meg resistor, your circuit is poorly formulated.  The current can be divided arbitrarily between the 10Meg resistor and your vams module.  The voltage on the "p" terminal of the module doesn't affect the current through it.  You could have V(p) = 10Meg * iref + vdd and I(<p>)=0 (all the current flows back through the resistor), or you could have V(p)=vdd (no current through the resistor, hence it all flows through the "p" terminal) -- or anything in between!

There's circular reasoning in your module.

Internally, the simulator knows that I(<p>) is the sum of all the currents of the branches terminating at "p"; but you've also set up equations such that the branch currents depend on I(<p>) -- and hence depend on themselves!!

Is there some reason you didn't like my approach,
 I(n1) <+ I(p) * ...
 I(n2) <+ I(p) * ...

The I(p) on the right-hand side creates a short from "p" to ground, thus making sure the module takes all the current available at the "p" terminal.