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Simulation of DC Offset due to LO Selfmixing (Read 1578 times)
m_h
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Simulation of DC Offset due to LO Selfmixing
Sep 01st, 2005, 4:50am
 
Hello everybody,
I am working on a gilbert cell mixer for direct conversion and I would like to simulate the DC Offset caused by LO self-mixing. I used QPSS analysis with 77 GHz(large) at LO port, and a 76.9 GHz(moderate)  signal and a 77GHz(moderate) blocker at RF port. I also applied a transient simulation to cross check the results. I observed the following behaviour:
In the transient simulation the IF output common mode voltage starts at e.g. 4.2 V and then ramps up to a steady state value of e.g. 4.8 V due to LO blocker at the RF port. Which seems reasonable.
The QPSS analysis yields as DC voltage at the IF output  of 4.2V. If I sweep the power level of the blocking signal the DC offset is still at 4.2V.
How can I set up the QPSS analysis to make this kind of simulations?
Thanks in advance for your help
Marcus
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