The Designer's Guide Community
Forum
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
May 6th, 2024, 7:18am
Pages: 1
Send Topic Print
How to reduce PLL jitter? (Read 2859 times)
vijay
Junior Member
**
Offline



Posts: 18

How to reduce PLL jitter?
Sep 15th, 2005, 4:42am
 
Hi,
I am trying to simulate a complimentry negative gm LC oscillator and use it in my PLL based synthesizer.I have a jitter measured through the process that Ken's paper describes.
What would be the ways to reduce the jitter if the value which I come across after the simulationdoes not suit my specification?
Back to top
 
 
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to editor@designers-guide.org. Consider submitting a paper or model.