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using transient analysis for stability checks (Read 16285 times)
Croaker
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using transient analysis for stability checks
Sep 11th, 2005, 9:24pm
 
Hi all, apart from the typical open loop gain plot to determine phase margin, I'm wondering about whether it's recommended to use a transient analysis to check for oscillation, as a sanity check...

I've compensated my op-amps and they have a decent phase margin.  Once I construct my circuit (a current mirror with op-amps for regulation), the DC analysis gives a typical current mirror iout vs. vout curve.  However, when I do a transient analysis and wiggle vout, the circuit starts to oscillate.

I'm guessing the circuit topology I've used may have some positive feedback but I haven't been able to figure out where I'm going wrong.  Is there a methodical way to check how the loop operates...?  

Anyhow, I know this wasn't that specific a post.  If you feel like taking a look I'd be happy to e-mail you a schematic (it's small).  It's not online, otherwise I'd provide a link. Sad

mwmurphyx@yahoo.com
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uncle_ezra
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Re: using transient analysis for stability checks
Reply #1 - Sep 12th, 2005, 1:04am
 
Yes it is always recommended to run transient analysis at the end for sanity check! What do you mean by you wiggle the output?
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Frank Wiedmann
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Re: using transient analysis for stability checks
Reply #2 - Sep 12th, 2005, 4:45am
 
An additional transient simulation to check loop stability is always a good idea in order to see if there are any nonlinear effects causing instability that the linear analysis will not find.

However, in your case, you will probably also find the instability with a proper loop gain simulation. I have seen circuits like yours go unstable before, sometimes depending on the load at the output of the current mirror.

The open-loop gain of an amplifier only tells you about stability in the case of resistive feedback, where you only have attenuation and no additional phase shift in the loop. In your circuit, you probably have additional components in your loop which are causing a phase shift or amplification.

I would recommend you to perform a stability (stb) analysis of your circuit in Spectre. Take an iprobe element from analogLib and place it somewhere in the loop, e.g. at the input or the output of the amplifier. The result should be independent of the position of the iprobe in the loop, you may also use this in order to check if your simulation setup is correct. Select the iprobe element as the Probe Instance in the stb setup form. The analysis works similar to an ac analysis, you will get the loop gain (with 180 degrees difference to the usual definition, see http://www.designers-guide.org/Forum/?board=circuit;action=display;num=112468832...), phase margin and gain margin as results. They will probably indicate that your circuit is unstable.
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Croaker
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Re: using transient analysis for stability checks
Reply #3 - Sep 12th, 2005, 5:09am
 
By wiggle the output, I mean I change it from something like 100 mV to 105 mV with a pulse source.

Thanks a lot guys!  One other thought I had was to simulate with ideal op-amp models, just to see if the circuit topology inherently uses positive feedback (which I don't think it does...)
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Croaker
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Re: using transient analysis for stability checks
Reply #4 - Sep 12th, 2005, 8:31am
 
Hmm, on a somewhat related note, is it bad to have a LHP zero near the open loop unity gain frequency?  It seems like it would improve the phase margin.  Does it have detrimental effects?

Marc
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Jess Chen
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Re: using transient analysis for stability checks
Reply #5 - Sep 12th, 2005, 10:51am
 
Placing a zero (an open loop zero) near the crossover frequency is a standard way to improve phase margin. See "lead-lag" compensation in any text book on classical control theory.  If you can adjust the overall gain independently, I know of no general detrimental effects caused by the lead-lag compensation.

-Jess

P.S. I agree with the idea of always checking AC analyses with transient analysis, and vice versa for that matter. The Nyquist criterion can be tricky sometimes, especially if the open loop system is unstable. I have also seen transient simuations that were falsely unstable. The instability appeared at the crossover frequency but the AC analysis predicted stability. Tighter numerical options showed the transient simulation to be stable, as predicted by the AC analysis.
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Croaker
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Re: using transient analysis for stability checks
Reply #6 - Sep 12th, 2005, 11:16am
 
Feedback theory usually talks about a transfer function between a voltage vin and vout.  

For the example I am working with, a current mirror, I'm not sure how a transfer function applies (and all the stability analysis) if the results you are interested in occur at the same node, i.e. observe the current for a given input voltage.  This would be what you typically do to find Rout, except the input is non-zero.  In this case I am looking at what happens to iout as vout changes.  

Is this a case where it makes sense to apply feedback theory?  I doesn't seem to fit as well with the normal block diagrams (A forward, Beta backward) as changing Iin or Vin on the input side of the mirror and observing what happens at the output.
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Jess Chen
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Re: using transient analysis for stability checks
Reply #7 - Sep 12th, 2005, 11:58am
 
I am not sure this is what you have but I'll take a chance. I'm assuming you are concerned about a load making the current mirror unstable. Let the output impedance of the current mirror be Zo. Let the load be Zl. The transfer function from short circuit current to load current is

Zo/(Zo+Zl), which can be written as

1/(1+T) where T = Zl/Zo.  T can be treated as a loop gain.

If |Zl|<<|Zo|, the current source is essentially ideal and life is good. As |Zl| approaches |Zo|, you must start thinking about stability and whether T violates the Nyquist stability criterion.
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Croaker
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Re: using transient analysis for stability checks
Reply #8 - Sep 12th, 2005, 12:24pm
 
That rings a bell...Blackman impedance stuff?

The specific problem I'm having is that I've got a current mirror using op-amps.  DC analysis says things look fine.  The AC open-loop gain analysis of the op-amps says they are compensated.  However, when I put the circuit together and run a transient analysis, the circuit oscillates.  I thought it might be because my circuit topology might be using positive feedback unbeknownst to me.  

So, I feed the mirror an input current and at the output I apply a voltage, vout.  In transient mode the circuit starts off where the DC operating point analysis says it should, but as soon as I vary vout, oscillation occurs.  Now, it might be the way I setup the test, or the simulator, but I think it's probably a circuit problem.

As you can tell, I'm crossing the gap from theory to practice, and it's a tad painful.  My goal is to figure out if there is positive feedback in my circuit and if so, figure out where it comes from.  Is there a simple test for this?

Has anyone seen the General Feedback Theorem stuff by Dr.Middlebrook from Caltech?  Seems useful!  http://ardem.com/gft_origin.asp
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Jess Chen
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Re: using transient analysis for stability checks
Reply #9 - Sep 12th, 2005, 6:07pm
 
I'm having a hard time visualizing your circuit. However, I would try conservative numerical options to see if the original transient response becomes stable. My experience with trapezoidal ringing (in SPICE) is that the ring frequency can coincide with the frequency where the phase hits 180 degrees, even though the AC analysis says the loop gain is less than unity at that point.

Off hand, it sounds like your op amps have more phase shift than you expect.  But another thing to try is to see if your op amps are stable by themselves.

I would probably proceed as you are doing. One nice thing about models is that you can surgically remove characteristics to eventually isolate the culprit.
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Croaker
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Re: using transient analysis for stability checks
Reply #10 - Sep 12th, 2005, 6:31pm
 
Jess, I can e-mail you the schematic if you feel like taking a look.  I'd greatly appreciate it if you can spot something I didn't or at least have a better picture of what I'm having trouble with.

As for the types of analysis, picture a simple current mirror.  There is an input current and an output voltage at the output node (drain of FET).  Right now I am varying that output voltage to see what happens.

The op-amps are stable by themselves.  They do have a zero which is supposed to improve the phase margin.  I also applied a step input to them and they didn't oscillate.

mwmurphyx@yahoo.com
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Jess Chen
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Re: using transient analysis for stability checks
Reply #11 - Sep 12th, 2005, 7:46pm
 
I should probably not download your schematic onto my office account. It's against company policy.  I'm not sure how much I can do with just a picture but if you have a pdf version of your schematic, you could e-mail it to my home e-mail. At least I'd have a better idea of the transfer function issue you described.

chennanga@yahoo.com

-Jess
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Croaker
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Re: using transient analysis for stability checks
Reply #12 - Sep 12th, 2005, 9:13pm
 
Cool, I re-evaluated my transient sim with ideal op-amps and it appears it's unstable due to a positive feedback topology!  Ouch.  

I'll send you the pic.  Much appreciated.
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Jess Chen
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Re: using transient analysis for stability checks
Reply #13 - Sep 13th, 2005, 8:45am
 
In looking over this thread, I see I actually got it confused with a previous one. I meant to post my initial response at another location. I've moved it to the right location. However, I am into it now and I am still willing to look at your schematic if you want to send it to me.

-Jess
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Jess Chen
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Re: using transient analysis for stability checks
Reply #14 - Sep 15th, 2005, 8:44am
 
Marc,
I received the figure you sent and I have several observations. Perhaps one of them helps.  Please give me a few minutes to complete this post. I must post it in phases because my editor blows everything away if I take too long to compose my response.

I see several interacting feedback loops. Perhaps the best way to proceed is to start with ideal conditions and then add non-ideal conditions one at a time.

1. Assuming the Vin and Vout nodes are driven and loaded with ideal voltage sources respectively, and that mosfets m1 and m2 have no coupling from drain to gate, you have two cascaded feedback loops. oa2 and m4 form the first and oa1 and m3 form the second. I would first determine if these two smaller loops are stable by themselves under these ideal conditions.

2. Drain to gate capacitance in m2 along with a finite output impedance in oa3 could introduce positive feedback into the oa2/m4 loop but a low oa3 output impedance probably makes the gain in that path negigible.

3. A finite source impedance driving Vin creates another feedback loop. This loop goes through the oa2/m4 loop, which is in parallel with the center wire. This loop and the m3/oa1 loop form two nested loops.

4. A finite load impedance at vout creates an opportunity for instability through the impedance interaction I mentioned in an earlier post.

It is clear the circuit has multiple loops. Low source, load, and oa output impedances decouples the loops but to quantify the amount of stability introduced by these assumptions I would either compute the closed loop poles directly or perform a sequential loop closure analysis.

The problem with computing the closed loop poles is that I don't completely trust the pole/zero analysis of existing simulators and the manual approach is fairly tedious. Simulators fit poles and zeros to transfer functions. (That means you must first identify a transfer function that does not hide internal RHP poles.) My experience with simulator pole/zero analysis is that the set of poles and zeros that match the transfer function is not unique and you may get a misleading set of poles/zeros.

Given the simulator constraints, I prefer the sequential loop closure procedure. However, you must apply it with strict, STRICT adherence to the Nyquist stability criterion. Furthermore, the conclusions only tell of absolute stability; assessment of relative stability can be tricky. The best way to draw some reasonable conclusions about relative stability is to start with the highest bandwidth loops and finish with the slowest loops. Hopefully nested loops are arranged with the fastest ones inside the slower ones. You start with all loops open, which may be hard if you have lots of interstage loading but Spectre's new stability analysis may help there. You assess the loop gain of the first loop with all others open. Whenever you encounter an unstable loop, record the number of RHP poles because another loop could stabilize the first loop if it's Nyquist plot encircles the -1,0 point counter clockwise enough times. With the first loop closed and all the rest open, assess the loop gain of the next loop. After you determine the number of RHP poles introduced by closing that loop, close that loop and proceed to the next loop. Each time you assess a loop, keep it closed while assessing subsequent loops. The common mistake made with this approach is to assess each loop with ALL others opened. You must assess each loop with previously assessed loops closed and unassessed loops open.

Sequential loop closures can be tedious but not as tedious as a manual pole/zero analysis. Furthermore, although relative stability can depend on the order in which you assessed and closed the loops, the procedure is compatible with the tools at hand and the final RHP pole count is accurate.

-Jess
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